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- removed 1-wire from sdb on designs with WRabbit
- doc updated

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+code commenting

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and some folders cleanup

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- added xwb_register_link to improve timing

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-added reg for the deactivation of tstamps storage from a particular channel, while in acquisition mode
-this version has chipscope

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/!\folder not yet integrated properly in project's structure/!\

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- added SVEC_FMC_TDC manual with registers mapping and operation instructions for driver developers

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- changed SPEC synthesis to ISE (was Synplify)
- general cleanup

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spec: removed dma; timestamps to be retrieved through wishbone (not stable yet; code needs bit of cleaning!)

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