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This is an archived project. Repository and other project resources are read-only.
fmc-projects
fmc-tdc
fmc-tdc-1ns-5cha-gw
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3b60a1ec
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Commit
3b60a1ec
authored
9 years ago
by
Tomasz Wlostowski
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top: updated synthesis descriptors
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5765c94d
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hdl/top/spec/synthesis_descriptor.vhd
+4
-4
4 additions, 4 deletions
hdl/top/spec/synthesis_descriptor.vhd
hdl/top/svec/synthesis_descriptor.vhd
+57
-57
57 additions, 57 deletions
hdl/top/svec/synthesis_descriptor.vhd
with
61 additions
and
61 deletions
hdl/top/spec/synthesis_descriptor.vhd
+
4
−
4
View file @
3b60a1ec
...
...
@@ -43,11 +43,11 @@ package synthesis_descriptor is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"wr_spec_tdc "
,
syn_commit_id
=>
"
00000000000000000000000000000000
"
,
syn_commit_id
=>
"
5765c94d3f0b118adcc9bfea880aca75
"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"000001
3
4"
,
syn_date
=>
x"201
40617
"
,
syn_username
=>
"
egousiou
"
);
syn_tool_version
=>
x"0000014
7
"
,
syn_date
=>
x"201
50522
"
,
syn_username
=>
"
twlostow
"
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
...
...
This diff is collapsed.
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hdl/top/svec/synthesis_descriptor.vhd
+
57
−
57
View file @
3b60a1ec
------------------------------------------------------------------------------
-- Title : TDC FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2015-04-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"wr_svec_tdc "
,
syn_commit_id
=>
"
00000000000000000000000000000000
"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000147"
,
syn_date
=>
x"20150
408
"
,
syn_username
=>
"twlostow "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"http://svn.ohwr.org/fmc-tdc "
);
end
package
synthesis_descriptor
;
------------------------------------------------------------------------------
-- Title : TDC FMC SVEC (Simple VME FMC Carrier) SDB descriptor
-- Project : TDC FMC (fmc-tdc-1ns-5cha)
-------------------------------------------------------------------------------
-- File : synthesis_descriptor.vhd
-- Author : Evangelia Gousiou
-- Company : CERN
-- Created : 2013-04-16
-- Last update: 2015-04-08
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: SDB descriptor for the top level of the FD on a SPEC carrier.
-- Contains synthesis & source repository information.
-- Warning: this file is modified whenever a synthesis is executed.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
STD_LOGIC_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"wr_svec_tdc "
,
syn_commit_id
=>
"
5765c94d3f0b118adcc9bfea880aca75
"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000147"
,
syn_date
=>
x"20150
522
"
,
syn_username
=>
"twlostow "
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"http://svn.ohwr.org/fmc-tdc "
);
end
package
synthesis_descriptor
;
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