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fmc-tdc-1ns-5cha-gw
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This is an archived project. Repository and other project resources are read-only.
fmc-projects
fmc-tdc
fmc-tdc-1ns-5cha-gw
Commits
2d00d3ef
Commit
2d00d3ef
authored
9 years ago
by
Tomasz Wlostowski
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fmc_tdc_wrapper: no need for cross-clocking IRQ signal after clock tree rewrite
parent
22139218
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hdl/top/spec/fmc_tdc_wrapper.vhd
+1
-15
1 addition, 15 deletions
hdl/top/spec/fmc_tdc_wrapper.vhd
with
1 addition
and
15 deletions
hdl/top/spec/fmc_tdc_wrapper.vhd
+
1
−
15
View file @
2d00d3ef
...
...
@@ -357,7 +357,7 @@ begin
slave_o
=>
cnx_master_in
(
c_slave_regs
),
-- Interrupt line from EIC
wb_irq_o
=>
fmc_eic_
irq
,
wb_irq_o
=>
irq
_o
,
-- Configuration of the DAC on the TDC mezzanine, non White Rabbit
acam_refclk_r_edge_p_i
=>
acam_refclk_r_edge_p
,
...
...
@@ -422,20 +422,6 @@ begin
direct_timestamp_o
=>
direct_timestamp
,
direct_timestamp_stb_o
=>
direct_timestamp_wr
);
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- Domains crossing: synchronization of the wb_ird_o from 125MHz to 62.5MHz
irq_pulse_synchronizer
:
process
(
clk_sys_i
)
begin
if
rising_edge
(
clk_sys_i
)
then
if
rst_sys_n_i
=
'0'
then
fmc_eic_irq_synch
<=
(
others
=>
'0'
);
else
fmc_eic_irq_synch
<=
fmc_eic_irq_synch
(
0
)
&
fmc_eic_irq
;
end
if
;
end
if
;
irq_o
<=
fmc_eic_irq_synch
(
1
);
end
process
;
U_DirectRD
:
fmc_tdc_direct_readout
port
map
(
...
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