fmc_tdc_mezzanine: forgot to re-connect direct timestamp output after implementing FIFO readout

hdl/rtl/fmc_tdc_mezzanine.vhd

@@ -478,6 +478,15 @@ begin
     end if;
   end process;
 
+  process(clk_tdc_i)
+  begin
+    if rising_edge(clk_tdc_i) then
+      direct_timestamp_stb_o <= timestamp_stb;
+      direct_timestamp_o <= timestamp;
+    end if;
+  end process;
+  
+                     
 
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