Added changes from Alvaro to *.xco files

ise/ipcore_dir/FIFO.xco

 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Tue Feb 12 16:08:05 2013
+# Xilinx Core Generator version 14.7
+# Date: Fri Aug 29 16:37:03 2014
 #
 ##############################################################
 #
@@ -22,16 +22,16 @@ SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
 SET designentry = VHDL
-SET device = xc6slx16
+SET device = xc6slx45t
 SET devicefamily = spartan6
 SET flowvendor = Other
 SET formalverification = false
 SET foundationsym = false
 SET implementationfiletype = Ngc
-SET package = csg324
+SET package = fgg484
 SET removerpms = false
 SET simulationfiles = Behavioral
-SET speedgrade = -2
+SET speedgrade = -3
 SET verilogsim = false
 SET vhdlsim = true
 # END Project Options
@@ -117,14 +117,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
 CSET fifo_implementation_wdch=Common_Clock_Block_RAM
 CSET fifo_implementation_wrch=Common_Clock_Block_RAM
 CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=14
+CSET full_threshold_assert_value=13
 CSET full_threshold_assert_value_axis=1023
 CSET full_threshold_assert_value_rach=1023
 CSET full_threshold_assert_value_rdch=1023
 CSET full_threshold_assert_value_wach=1023
 CSET full_threshold_assert_value_wdch=1023
 CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=13
+CSET full_threshold_negate_value=12
 CSET id_width=4
 CSET inject_dbit_error=false
 CSET inject_dbit_error_axis=false
@@ -163,7 +163,7 @@ CSET programmable_empty_type_rdch=Empty
 CSET programmable_empty_type_wach=Empty
 CSET programmable_empty_type_wdch=Empty
 CSET programmable_empty_type_wrch=Empty
-CSET programmable_full_type=No_Programmable_Full_Threshold
+CSET programmable_full_type=Single_Programmable_Full_Threshold_Constant
 CSET programmable_full_type_axis=Full
 CSET programmable_full_type_rach=Full
 CSET programmable_full_type_rdch=Full
@@ -216,4 +216,4 @@ CSET wuser_width=1
 MISC pkg_timestamp=2011-10-22T06:08:52Z
 # END Extra information
 GENERATE
-# CRC: 9755c96c
+# CRC: e0f1f870

ise/ipcore_dir/tlu_event_fifo.xco

 ##############################################################
 #
-# Xilinx Core Generator version 13.4
-# Date: Thu Dec  6 12:13:31 2012
+# Xilinx Core Generator version 14.7
+# Date: Thu Aug 28 15:34:30 2014
 #
 ##############################################################
 #
@@ -22,16 +22,16 @@ SET asysymbol = true
 SET busformat = BusFormatAngleBracketNotRipped
 SET createndf = false
 SET designentry = VHDL
-SET device = xc6slx16
+SET device = xc6slx45t
 SET devicefamily = spartan6
 SET flowvendor = Other
 SET formalverification = false
 SET foundationsym = false
 SET implementationfiletype = Ngc
-SET package = csg324
+SET package = fgg484
 SET removerpms = false
 SET simulationfiles = Behavioral
-SET speedgrade = -2
+SET speedgrade = -3
 SET verilogsim = false
 SET vhdlsim = true
 # END Project Options
@@ -53,7 +53,7 @@ CSET clock_enable_type=Slave_Interface_Clock_Enable
 CSET clock_type_axi=Common_Clock
 CSET component_name=tlu_event_fifo
 CSET data_count=false
-CSET data_count_width=12
+CSET data_count_width=14
 CSET disable_timing_violations=false
 CSET disable_timing_violations_axi=false
 CSET dout_reset_value=0
@@ -117,14 +117,14 @@ CSET fifo_implementation_wach=Common_Clock_Block_RAM
 CSET fifo_implementation_wdch=Common_Clock_Block_RAM
 CSET fifo_implementation_wrch=Common_Clock_Block_RAM
 CSET full_flags_reset_value=1
-CSET full_threshold_assert_value=4080
+CSET full_threshold_assert_value=16000
 CSET full_threshold_assert_value_axis=1023
 CSET full_threshold_assert_value_rach=1023
 CSET full_threshold_assert_value_rdch=1023
 CSET full_threshold_assert_value_wach=1023
 CSET full_threshold_assert_value_wdch=1023
 CSET full_threshold_assert_value_wrch=1023
-CSET full_threshold_negate_value=4079
+CSET full_threshold_negate_value=15999
 CSET id_width=4
 CSET inject_dbit_error=false
 CSET inject_dbit_error_axis=false
@@ -141,7 +141,7 @@ CSET inject_sbit_error_wach=false
 CSET inject_sbit_error_wdch=false
 CSET inject_sbit_error_wrch=false
 CSET input_data_width=64
-CSET input_depth=4096
+CSET input_depth=16384
 CSET input_depth_axis=1024
 CSET input_depth_rach=16
 CSET input_depth_rdch=1024
@@ -150,7 +150,7 @@ CSET input_depth_wdch=1024
 CSET input_depth_wrch=16
 CSET interface_type=Native
 CSET output_data_width=32
-CSET output_depth=8192
+CSET output_depth=32768
 CSET overflow_flag=false
 CSET overflow_flag_axi=false
 CSET overflow_sense=Active_High
@@ -174,7 +174,7 @@ CSET rach_type=FIFO
 CSET rdch_type=FIFO
 CSET read_clock_frequency=1
 CSET read_data_count=true
-CSET read_data_count_width=14
+CSET read_data_count_width=16
 CSET register_slice_mode_axis=Fully_Registered
 CSET register_slice_mode_rach=Fully_Registered
 CSET register_slice_mode_rdch=Fully_Registered
@@ -209,11 +209,11 @@ CSET write_acknowledge_flag=false
 CSET write_acknowledge_sense=Active_High
 CSET write_clock_frequency=1
 CSET write_data_count=true
-CSET write_data_count_width=13
+CSET write_data_count_width=15
 CSET wuser_width=1
 # END Parameters
 # BEGIN Extra information
 MISC pkg_timestamp=2011-10-22T06:08:52Z
 # END Extra information
 GENERATE
-# CRC:  9ee55f2
+# CRC: 9008abaa

scripts/build_bitstream.sh

@@ -10,7 +10,7 @@
 # David Cussans, December 2013
 #
 
-export BOARD_TYPE=sp601
+export BOARD_TYPE=sp605
 export ISE_VER=ise14
 
 export FW_WORKSPACE=`pwd`

scripts/setup_workspace.sh

@@ -14,7 +14,7 @@
 
 export FW_WORKSPACE=`pwd`
 echo "Current directory = " $FW_WORKSPACE
-export BOARD_TYPE=sp601
+export BOARD_TYPE=sp605
 export ISE_VER=ise14
 export VERSION=trunk