Hacking on timing constraints.

N.B. Also need to edit *.dep files to put TLU_enclustra_v1e.xdc *after* enclustra_ax3_pm3.tcl

After sorting out some of the timing problems now get a firmware image that "works"

AIDA_tlu/projects/TLU_v1e/firmware/ucf/TLU_enclustra_v1e.xdc

@@ -125,12 +125,44 @@ set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
 
 
 
+# set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
+
+
 create_clock -period 25.000 -name sysclk_40_i_p -waveform {0.000 12.500} [get_ports sysclk_40_i_p]
-set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
-set_input_delay -clock [get_clocks [get_clocks -of_objects [get_pins I4/pll_base_inst/CLKOUT0]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
-set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
 
+create_clock -period 6.250 -name s_clk160 -waveform {0.000 3.125} [get_pins I4/pll_base_inst/CLKOUT1]
+create_clock -period 3.125 -name s_clk320 -waveform {0.000 1.562} [get_pins I4/pll_base_inst/CLKOUT0]
+create_clock -period 32.000 -name clk_ipb_i -waveform {0.000 16.000} [get_pins infra/clocks/bufgipb/I]
 
+# set_clock_groups -asynchronous -group [list [get_clocks sysclk]] -group [list  [get_clocks sysclk_40_i_p]]
 
+set_clock_groups -asynchronous -group [list [get_clocks clk_ipb_i] [get_clocks sysclk]] -group [list [get_clocks s_clk160] [get_clocks sysclk_40_i_p]]
 
 
+#set_input_delay -clock [get_clocks s_clk320]]] -rise -min 0.300 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
+#set_input_delay -clock [get_clocks s_clk320]]] -rise -max 1.400 [get_ports -regexp -filter { NAME =~  ".*thresh.*" && DIRECTION == "IN" }]
+
+set_input_delay -clock [get_clocks s_clk160] -min -add_delay 3.100 [get_ports {busy_i[*]}]
+set_input_delay -clock [get_clocks s_clk160] -max -add_delay 3.700 [get_ports {busy_i[*]}]
+set_input_delay -clock [get_clocks s_clk160] -min -add_delay 3.100 [get_ports {dut_clk_i[*]}]
+set_input_delay -clock [get_clocks s_clk160] -max -add_delay 3.700 [get_ports {dut_clk_i[*]}]
+set_input_delay -clock [get_clocks s_clk320] -clock_fall -min -add_delay 1.600 [get_ports {threshold_discr_p_i[*]}]
+set_input_delay -clock [get_clocks s_clk320] -clock_fall -max -add_delay 1.850 [get_ports {threshold_discr_p_i[*]}]
+set_input_delay -clock [get_clocks clk_ipb_i] -min -add_delay 15.100 [get_ports i2c_scl_b]
+set_input_delay -clock [get_clocks clk_ipb_i] -max -add_delay 17.200 [get_ports i2c_scl_b]
+set_input_delay -clock [get_clocks clk_ipb_i] -min -add_delay 15.100 [get_ports i2c_sda_b]
+set_input_delay -clock [get_clocks clk_ipb_i] -max -add_delay 17.100 [get_ports i2c_sda_b]
+set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {cont_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {cont_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {dut_clk_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {dut_clk_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {spare_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {spare_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports {triggers_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports {triggers_o[*]}]
+set_output_delay -clock [get_clocks s_clk160] -min -add_delay -0.300 [get_ports gpio]
+set_output_delay -clock [get_clocks s_clk160] -max -add_delay 5.100 [get_ports gpio]
+set_output_delay -clock [get_clocks clk_ipb_i] -min -add_delay -1.800 [get_ports i2c_scl_b]
+set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_scl_b]
+set_output_delay -clock [get_clocks clk_ipb_i] -min -add_delay -1.800 [get_ports i2c_sda_b]
+set_output_delay -clock [get_clocks clk_ipb_i] -max -add_delay 30.100 [get_ports i2c_sda_b]