Checking in fixes to triggerInputs - should now provide pulse on trigger_o and...

Checking in fixes to triggerInputs - should now provide pulse on trigger_o and trigger_times_o, which had become disconnected

hdl/common/triggerInputs_rtl.vhd

@@ -54,23 +54,23 @@ ENTITY triggerInputs IS
       g_NUM_INPUTS : natural := 1
    );
    PORT( 
-      cfd_discr_p_i         : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
-      cfd_discr_n_i       : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);
-      clk_4x_logic          : IN     std_logic;                                     -- ! Rising edge active
-      strobe_4x_logic_i     : IN     std_logic;                                     -- ! Pulses high once every 4 cycles of clk_4x_logic
-      threshold_discr_p_i   : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! inputs from threshold comparators
-      threshold_discr_n_i : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! inputs from threshold comparators
-      trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  -- ! trigger arrival time ( w.r.t. logic_strobe)
-      trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when trigger active
-      trigger_debug_o     : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);    -- ! Copy of input trigger level. High bits CFD, Low threshold
-		edge_rising_times_o   : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  -- ! edge arrival time ( w.r.t. logic_strobe)
-		edge_falling_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  -- ! edge arrival time ( w.r.t. logic_strobe)
-      edge_rising_o         : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when rising edge
-		edge_falling_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    -- ! High when falling edge
+      cfd_discr_p_i         : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--! Inputs from constant-fraction discriminators
+      cfd_discr_n_i       : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO0);--! Input from CFD
+      clk_4x_logic          : IN     std_logic; --! Rising edge active. By default = 4*40MHz = 160MHz
+      strobe_4x_logic_i     : IN     std_logic;                                     --! Pulses high once every 4 cycles of clk_4x_logic
+      threshold_discr_p_i   : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! inputs from threshold comparators
+      threshold_discr_n_i : IN     std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! inputs from threshold comparators
+      trigger_times_o     : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! trigger arrival time ( w.r.t. logic_strobe)
+      trigger_o           : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);--!  Goes high on leading edge of trigger, in sync with clk_4x_logic_i
+      trigger_debug_o     : OUT    std_logic_vector ( ((2*g_NUM_INPUTS)-1) DOWNTO 0);    --! Copy of input trigger level. High bits CFD, Low threshold
+      edge_rising_times_o   : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+      edge_falling_times_o  : OUT    t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+      edge_rising_o         : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0); --! High when rising edge. Syncronous with clk_4x_logic_i
+      edge_falling_o        : OUT    std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
       ipbus_clk_i           : IN     std_logic;
       ipbus_reset_i         : IN     std_logic;
-      ipbus_i               : IN     ipb_wbus;                                      -- Signals from IPBus core to slave
-      ipbus_o               : OUT    ipb_rbus;                                      -- signals from slave to IPBus core
+      ipbus_i               : IN     ipb_wbus;                                      --! Signals from IPBus core to slave
+      ipbus_o               : OUT    ipb_rbus;                                      --! signals from slave to IPBus core
       clk_16x_logic_i       : IN     std_logic;                                     --! 640MHz clock ( 16x 40MHz )
       strobe_16x_logic_i    : IN     std_logic                                      --! Pulses one cycle every 4 of 16x clock.
    );
@@ -84,13 +84,13 @@ ARCHITECTURE rtl OF triggerInputs IS
   
   signal s_rst_iserdes, s_rst_iserdes_ipb : std_logic := '0'; --! Reset ISERDES and calibrate IODELAY
   
-  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  -- ! inputs from comparator
+  signal s_threshold_discr_input , s_cfd_discr_input : std_logic_vector(g_NUM_INPUTS-1 downto 0);  --! inputs from comparator
 
   type t_deserialized_trigger_data_array is array ( natural range <> ) of std_logic_vector(7 downto 0); --
 
   signal s_deserialized_threshold_data , s_deserialized_cfd_data : t_deserialized_trigger_data_array(g_NUM_INPUTS-1 downto 0);
 
-  signal s_serdes_reset                   : std_logic := '0';  -- ! Take high to reset serdes and initiate IODELAY calibration
+  signal s_serdes_reset                   : std_logic := '0';  --! Take high to reset serdes and initiate IODELAY calibration
 
   signal s_cfd_trigger_times              : t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);
   
@@ -101,7 +101,12 @@ ARCHITECTURE rtl OF triggerInputs IS
   signal s_CFD_previous_late_bit          : std_logic_vector(g_NUM_INPUTS-1 downto 0) := (others => '0');  -- last bit to arrive from previous 4
   
   signal s_ipbus_ack                      : std_logic := '0';  -- used to produce a delayed IPBus ack signal
-  
+
+  signal s_edge_rising_times:   t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_falling_times:  t_triggerTimeArray (g_NUM_INPUTS-1 DOWNTO 0);  --! edge arrival time ( w.r.t. logic_strobe)
+  signal s_edge_rising:         std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when rising edge
+  signal s_edge_falling:        std_logic_vector (g_NUM_INPUTS-1 DOWNTO 0);    --! High when falling edge
+ 
 BEGIN
 
   ipbus_write: process (ipbus_clk_i)
@@ -172,13 +177,25 @@ BEGIN
         clk_4x_logic_i      => clk_4x_logic,
         strobe_4x_logic_i   => strobe_4x_logic_i,
         deserialized_data_i => s_deserialized_threshold_data(triggerInput) & s_threshold_previous_late_bit(triggerInput),
-        first_rising_edge_time_o => edge_rising_times_o(triggerInput), --trigger_times_o(triggerInput),
-        last_falling_edge_time_o => edge_falling_times_o(triggerInput), --open,
-        rising_edge_o       => edge_rising_o(triggerInput), --trigger_o(triggerInput),
-        falling_edge_o      => edge_falling_o(triggerInput),
+        first_rising_edge_time_o => s_edge_rising_times(triggerInput), 
+        last_falling_edge_time_o => s_edge_falling_times(triggerInput), 
+        rising_edge_o       => s_edge_rising(triggerInput), 
+        falling_edge_o      => s_edge_falling(triggerInput),
         multiple_edges_o    => open
         );
-		  
+
+    -- The leading edge may be a high-->low or a low-->high transition (
+    -- depending on polarity of input signal. ). For now assume that leading
+    -- edge is low-->high and connect trigger times and trigger output accordingly.
+    -- In the future have this selectable.
+    edge_rising_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+    edge_falling_times_o(triggerInput) <= s_edge_falling_times(triggerInput);
+    edge_rising_o(triggerInput) <= s_edge_rising(triggerInput);
+    edge_falling_o(triggerInput) <= s_edge_falling(triggerInput);
+    trigger_times_o(triggerInput) <= s_edge_rising_times(triggerInput);
+    trigger_o(triggerInput) <= s_edge_rising(triggerInput);
+    
+    
     CFDInputBuffer: IBUFDS
       generic map (
         DIFF_TERM        => true,