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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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YAM is a micro-controller core aiming at simple yet fast IO sequencing with integer processing capabilities. YAM parameters may be assigned to fit many applications. The data width is scalable from 8 to any value (like 32 or larger) size.
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xTCAprojects shows the MTCA and uTCA boards that are developed in the Open Hardware Repository context. Keywords: MTCA.4, uTCA, AMC, MCH.
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Control of instrumentation over a White Rabbit network. Define and implement a standardized communication protocol for instrumentation over a White Rabbit network (precise synchronization and timestamping; remote control and test sequence programming; message exchanging and event distribution).
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White Rabbit Switch WRS-3/18 (hardware version 3.4) with the low-jitter daughterboard integrated. More info at the Wiki page
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The aim of the board is to improve the performance of the WR Switch using an external PLL and a new VCTCXO. More info at the Wiki page
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Fanless version of the White Rabbit Switch WRS-3/18 (hardware version 3.4) with the low-jitter daughterboard integrated. More info at the Wiki page
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White Rabbit Switch WRS-3/18 (hardware version 3.4) with modified SCB prepared for the low-jitter daughterboard and modified backplane. Commercially available. More info at the Wiki page
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WRAP, White RAbbit Pluggable, is a plug-in board providing easy-to-use WR functionality. Among others it provides direct 10MHz and PPS (pulse per second) outputs.
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wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:
- Automatically allocated memory layout
- VHDL/Verilog code for the slave module
- C header files for driver development - Nice HTML documentation
Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2
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A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page
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A project to host all software and hardware developments related to testing the White Rabbit switch.
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Development of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor. More info at the Wiki page
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This project covers the hardware development of version 4 of the White Rabbit switch (WRS-v4). More info at the Wiki page
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This project covers the hardware development of the White Rabbit switch.
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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This project contains all the HDL gateware necessary for the FPGA of the WR switch.
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