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PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

The robustness of a White Rabbit Network (WRN) is a broad subject covering methods (HW & SW) which enable to increase overall reliability of a WR-based system. This includes Forward Error Correction (FEC), Quality of Service (QoS) assurance, support of network redundancy, proper network design, thorough diagnostics, and increasing the reliability of network components (i.e. switches, nodes). Here, these methods are described and their implementation sources gathered.

This is a port of an older Linux ptpd to support White Rabbit extensions and run both in hosted and freestanding environment. In the future we plan to replace it with PPSI, which has a much better design, but ptp-noposix is currently working pretty well despite being difficult to maintain.

Test. May be deleted.

A fully open electronic watch project featuring an integrated GPS receiver. More info at the Wiki page

Powerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page

The open-source HEV ventilator implements the modes PC-A/C, PC-A/C-PRVC, PC-PSV and CPAP More info at the Wiki page

Open Breath lung ventilator. It is developed to be low-cost, scalable and easily manufactured. It can be used in Pressure and Volume Control, SIMV+PS and CPAP functions. More info at the Wiki page

High-resolution frequency/phase-microstepper for timing laboratories. More info at the Wiki page

TiCkS is a flexible White Rabbit based time-stamping board. It is based on the SPEC board developed for the CTA collaboration. It provides an interface to a CTA camera (Inputs: Read-out Trigger signals, Busy Trigger), (Outputs: PPS signal , 10MHz clock, External trigger signal).

More info at the Wiki page

This is a PCB-design + Arduino firmware for an Ethernet-controlled 1:8 RF-multiplexer. It allows selecting as output one of eight input-channels, as commonly used e.g. in timing-laboratories when one wants to measure many RF-sources (clock outputs like 1PPS or 10MHz) with a single instrument (frequency or time-interval counter). The design is for two independent MUX-boards to fit in a 1U 19” rack enclosure. For more information, see the wiki

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

PCIe to VME bridge. More info at the Wiki page

Data centre environmental sensor - Dust, Temperature, Relative Humidity, Fan - Serial 1 channel - version 1. An environmental sensor for Data Centers that continuously measures airborne particle density in high airflow as well as temperature and relative humidity. It can control its fan speed if needed (PWM controlled fans) and monitors FAN rotational speed (tachometer equipped fans) for precise airflow control and monitoring. It is close to maintenance free and can be integrated in compact enclosures (for example tape drive tray or even an ATX PSU case...). More info at the Wiki page

A VHDL core for a PCI slave. The other side behaves like a Wishbone master.

More info at the Wiki page

EPICS support for Wishbone peripherals: This project consist of a Generic EPICS IOC AsynDriver to support wishbone peripheral. It include the following features:

Driver for X1052, Gennum, Etherbone WB master. Direct access to any register in the wishbone bus Auto-generation of EPICS Database file using wbgen2 Automatic real number convertion (2 complements, fixed point, signess) using .wb file Support for WR Core and other internal bus protocols (i2c, spi, etc.)

More info at the Wiki page

Gateware for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

A fully operational stand-alone FMC Delay card based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption. More info at the Wiki page

Etherbone is an FPGA-core that connects Ethernet to internal on-chip wishbone buses permitting any core to talk to any other across Ethernet.