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Active 32/64 channels 19" patch panel for FPGA boards, with robust 5V TTL I/Os, configurable through I²C and USB-C. More info at the Wiki page

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

A front-end PCI board with LEMO connectors to interface with the GPIO interconnect pins of the SIS1160 FMC carrier. More info at the Wiki page

DI/OT Peripheral Board Loop-back. More info at the Wiki page

Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

The Electronics Design project gives helpful entry points for electronics engineers. VHDL coding, design reviews, components, production, assembly and testing are some subjects. More info at the Wiki page

FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page

White Rabbit Trigger Distribution project. More info at the Wiki page

pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page

WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems. Cryogenics, Power Converters, Beam Instrumentation and other critical systems are using WorldFIP for the exchange of data between their sensors and actuators and the control and supervision level. With Alstom phasing out WorldFIP support in 2009, it was decided to insource this technology at CERN.

The PFC is a 4-lane PCIe carrier for a single VITA 57 (FMC) mezzanine. It has many memory and clocking resources and supports the White Rabbit timing and control network. For more details please refer to the Wiki pages. *Warning. This project is on hold. Refer to the SPEC*

The VFC is a VME carrier for two VITA 57 (FMC) mezzanines. For more details please refer to the wiki pages. Obsolete project. Replaced by VFC-HD.

FMCprojects shows the FMC Mezzanine and Carrier boards that are developed in the Open Hardware Repository context. Furthermore it gives useful data helping you to design modules complying to this VITA 57.1 standard. This actually is not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project.

FMC Projects Wiki home page

FMC DAC 10M 16b 4cha: 16-bit 10Ms/s DAC card in FMC form-factor. Four channels with an output range of +/-10V. Three trigger inputs (start, pause and stop), common to the four outputs.

Cancelled project.

Corelib - Project to share generic HDL cores.

OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page

FmcDIO16chTTLa is a 2x 8-bit port digital IO card in FMC form-factor. Each 8-bit port can be configured individually as input or output. IOs are TTL compatible. Additional test features can be mounted on the PCB. Project on hold.

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2

A VHDL core for a VME64x slave. The other side behaves like a Wishbone master.

More info at the Wiki page

FmcAdc200k16b11cha is an 11 channel 200kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. The input voltage range is settable to /-10V or/-5V. The input impedance is 1MOhm.