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Pascal Bos / Hdlmake
GNU General Public License v3.0 onlyTool for generating multi-purpose makefiles for FPGA projects.
Main features:
makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefilesHdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page
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A VHDL core for a PCI slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
OpenBreath / Open Breath Lung Ventilator
CERN Open Hardware Licence Version 2 - Strongly ReciprocalOpen Breath lung ventilator. It is developed to be low-cost, scalable and easily manufactured. It can be used in Pressure and Volume Control, SIMV+PS and CPAP functions. More info at the Wiki page
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Projects / AIDA-2020 TLU - Hardware
CERN Open Hardware Licence v1.2Updated -
Software to support the fmc-adc-100m14b4cha mezzanine, including Linux device driver, library and test program.
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A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor.
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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Introductory SoC course with reference designs based on the Xilinx Vitis Unified Software Development Platform and targeted to the Xilinx Zynq UltraScale+ MPSoC. More info at the Wiki page
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Projects / 3DMASK - 3D printed mask
CERN Open Hardware Licence Version 2 - PermissiveThis open-source 3DMASK offers a FFP2-level protection with the right filter material. It can be produced by anybody in possession of a 3D printer. More info at the Wiki page.
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The Face Shield, made only for COVID-19 protection, can be worn directly or can be put on safety helmets. The FaceShield is developed under the CERN against COVID-19 program. More info at the Wiki page
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VentilatorPAL is a high-quality and low-cost, open source ventilator. More info at the Wiki page
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OpenBreath / Open Breath PEP Whistle
CERN Open Hardware Licence Version 2 - Strongly ReciprocalUpdated -
Intel Arria V based VME64x carrier for one high pin count FMC with six SFP connectors, DDR3 memory and clocking resources to support White Rabbit. For more details please refer to the wiki pages.
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pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page
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A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.
The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.
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The uRV (Micro RISC-V) core is a small-sized implementation of a 32-bit RISC-V core, targeted specifically at FPGAs. More info at the Wiki page
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FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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