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YAM is a micro-controller core aiming at simple yet fast IO sequencing with integer processing capabilities. YAM parameters may be assigned to fit many applications. The data width is scalable from 8 to any value (like 32 or larger) size.

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Testing.

pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page

The OpenDSO is a bench top oscilloscope, built on top of an extensible Zynq-based platform. Features: 2x100 MS/s (basic frontend), extendable to 4x1GS/s or 2x2GS/s; Zynq 7000 FPGA, 512 MB RAM; 8" multitouch display with Qt GUI

The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Software.

A bridge between the local bus of the Gennum GN4124 (PCIe to local bus bridge) and Wishbone.

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor.

VME projects are sub-projects of this ohwr project. See all sub-projects for more information.

Study of the “Open Hardware Initiative” at CERN with a focus on the technologies of participation that were mobilized to assemble critical infrastructure for basic research in high energy physics.

The DAPHNE front end board is a piece of hardware that digitizes the output signal from one of the systems of the far detector in the DUNE experiment. For more information, see the wiki

COM Express based PXIe system controller. COM Express Compact Pin-out type 6, 16-lane PCIe GEN3. PXIe trigger line on front-panel. More info at the Wiki page

Fmc-adc-iso-400k18b4cha is a 4 channel 400kSps 18 bit ADC low pin count FPGA Mezzanine Card (VITA 57). The ground reference used for the analog inputs and the ADC is isolated from the ground reference of the FMC connector. Digital Isolators included allow the data transmission between two isolated areas. Voltage Bias between two grounds of up to 1kV can be applied, which is measured with a 100MOhm resistor connected between two grounds and an additional 10 bit ADC. Analog input voltage ranges: /-5V,/-10V. More info at the Wiki page

FMC thermocouple card interfacing with zQSFP+ to samc-temp-thcpl-20ch which connects 20 single-ended K-type or N-type thermocouple channels. Used in SAMbuCa project. More info at the Wiki page

EPICS support for Wishbone peripherals: This project consist of a Generic EPICS IOC AsynDriver to support wishbone peripheral. It include the following features:

Driver for X1052, Gennum, Etherbone WB master. Direct access to any register in the wishbone bus Auto-generation of EPICS Database file using wbgen2 Automatic real number convertion (2 complements, fixed point, signess) using .wb file Support for WR Core and other internal bus protocols (i2c, spi, etc.)

More info at the Wiki page

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.

More info at the Wiki page

Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page

Software support for the SPEC board, including kernel and user-space Linux code. The package also include the fmc-bus driver, which is expected to be used by other carriers as well.

An FMC for clock & data recovery from optical sources.