Explore projects

A fully open electronic watch-like device that will signal a too high-level of UV light. It is meant for people with a highly sensitive skin. More info at the Wiki page

A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor. More info at the Wiki page

Fmc-adc-iso-400k18b4cha is a 4 channel 400kSps 18 bit ADC low pin count FPGA Mezzanine Card (VITA 57). The ground reference used for the analog inputs and the ADC is isolated from the ground reference of the FMC connector. Digital Isolators included allow the data transmission between two isolated areas. Voltage Bias between two grounds of up to 1kV can be applied, which is measured with a 100MOhm resistor connected between two grounds and an additional 10 bit ADC. Analog input voltage ranges: /-5V,/-10V. More info at the Wiki page

A low cost potentiostat circuit to perform electrochemistry experiments. The system may be driven by a Teensy card from PJRC (Arduino IDE) or by power supplies, More info at the Wiki page

A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.

Production and functional tests for PXIe controller COM Express based. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).

Radiation tolerant LED luminaires. Currently in production with two manufacturers. More info at the Wiki page

The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function uses a 1ppm 20-Bit DAC (AD5791) as a reference and can be programmed as a differential voltage source. The card also includes 8 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.

A VME rear transition module providing 24 Dry Contact Inputs. Dry contact switch connecting 24V to ground (limited to 20mA). Uses the SVEC as front-module. More info at the Wiki page CANCELLED PROJECT

The DAPHNE front end board is a piece of hardware that digitizes the output signal from one of the systems of the far detector in the DUNE experiment. For more information, see the wiki

High performance pulse and frequency distribution amplifier for time and frequency metrology. The pulse distribution board is an 1:8-channel (1 Hz and up) logic-level distribution amplifier, while the frequency distribution board is an 1:8-channel sine-wave (1-30 MHz) distribution amplifier. Two 1:8 boards fit side-by-sides in a 1U 19" rack enclosure, with either BNC or SMA connectors.

For more information, see the wiki

Study of the “Open Hardware Initiative” at CERN with a focus on the technologies of participation that were mobilized to assemble critical infrastructure for basic research in high energy physics.

Hardware design of FMC ADC 400k 18b 4cha iso. Includes schematics, PCB layout and manufacturing files.

SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page

Data centre environmental sensor - Dust, Temperature, Relative Humidity, Fan - Serial 1 channel - version 1. An environmental sensor for Data Centers that continuously measures airborne particle density in high airflow as well as temperature and relative humidity. It can control its fan speed if needed (PWM controlled fans) and monitors FAN rotational speed (tachometer equipped fans) for precise airflow control and monitoring. It is close to maintenance free and can be integrated in compact enclosures (for example tape drive tray or even an ATX PSU case...). More info at the Wiki page

Gateware (HDL design) for PandABox is common between all platforms using the PandABlocks framework and is developed on Github:

PandABlocks-FPGA Github repository

E-bone first aims at interfacing an FPGA based PCIe Endpoint core to a collection of other cores. The E-bone release contains a number of general purpose cores within that scope. E-bone specifications cater for both a Control Interconnect and a Fast Transmitter. The Control Interconnect defines a 32 bit wide interconnection between a number of masters and slaves. The Fast Transmitter is a one way path (up to 256 bit wide) aiming at dumping large data sets to the root complex. E-bone is nevertheless not restricted to PCIe interfacing and may be used for developing sub-systems in others environments.

More info at the Wiki page