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VHDL coding style document to be used at ohwr.org The project contains also a tool to automatically check the coding style. More info at the Wiki page

FmcDIO16chTTLa is a 2x 8-bit port digital IO card in FMC form-factor. Each 8-bit port can be configured individually as input or output. IOs are TTL compatible. Additional test features can be mounted on the PCB. Project on hold.

Firmware(gateware) for FPGA on AIDA-Innova TLU ( AIDAInnova_TLU )

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

Hardware and software (libraries and GUI) to implement the SFF-8472 standard “Diagnostic Monitoring Interface for Optical Transceivers”. The hardware implements four SFP+s that can be exercised in parallel. To access the I2C interfaces a USB to I2C chip is used. More info at the Wiki page

The CTR FMC is an FMC card that can be used, in conjunction with the Simple PCIe FMC carrier (SPEC), to design a General Machine Timing (GMT) Receiver. More info at the Wiki page

PandA Motion Project is a collaboration between SOLEIL and DIAMOND to upgrade their “Position and Acquisition” processing platform. PandA will provide a common encoder processing platform based on Zynq 7030 and supporting multiple encoder standards (incremental, SSI, BISS...). It will deliver synchronous triggering and data capture capabilities.

More info at the Wiki page

Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

A fully open electronic watch-like device that will signal a too high-level of UV light. It is meant for people with a highly sensitive skin. More info at the Wiki page

Fmc-adc-iso-400k18b4cha is a 4 channel 400kSps 18 bit ADC low pin count FPGA Mezzanine Card (VITA 57). The ground reference used for the analog inputs and the ADC is isolated from the ground reference of the FMC connector. Digital Isolators included allow the data transmission between two isolated areas. Voltage Bias between two grounds of up to 1kV can be applied, which is measured with a 100MOhm resistor connected between two grounds and an additional 10 bit ADC. Analog input voltage ranges: /-5V,/-10V. More info at the Wiki page

Tool for generating multi-purpose makefiles for FPGA projects.

Main features:

makefile generation for: fetching modules from repositories simulating HDL projects synthesizing HDL projects synthesizing projects remotely (keeping your local resources free) generating multi-vendor project files (no clicking in the IDE!) many other things without involving make and makefiles

Hdlmake supports modularity, scalability, revision control systems. Hdlmake can be run on any Linux or Windows machine with any HDL More info at the Wiki page

PHASE (Portable Hardware Analyzer with Sharing Explorer) aims at unifying hardware debugging in a single tool. From the host machine, a user may graphically interconnect components to describe the connection between his computer and the target device to debug. For example, a USB JTAG cable might be the root node, connected to an Arria2 development board with a CPLD and an FPGA, containing a LM32 processor.

Wherever possible, PHASE fetches design descriptions from the internet based on the detected JTAG IDCODEs, USB vendor IDs, or PnP BUS information. In the preceding example, each step of the chain would be automatically detected. The USB cable from the vendor+product codes, the FPGA from the JTAG IDCODE and the LM32 from the Arria2's sld hub. The user would now be presented with read/write access to the data and instruction buses for visual inspection or firmware loading. Furthermore, the user could launch gdb to halt and single-step the embedded LM32 CPU.

If a device is not yet described, the user may assemble a driver out of the reusable software components. For example, an Altera USB-Blaster driver is just a FTDI device chained with a byte packeter and a JTAG bit banger. Once the design has been graphically assembled, it is automatically scanned for attached JTAG devices and the USB cable design is shared online with any future users of the same cable.

The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).

FMC thermocouple card interfacing with zQSFP+ to samc-temp-thcpl-20ch which connects 20 single-ended K-type or N-type thermocouple channels. Used in SAMbuCa project. More info at the Wiki page

Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page

AFCKU is dual FMC carrier in AMC format based on Kintex Ultrascale SoC devices. It supports White Rabbit and RTM modules. More info at the Wiki page.

The FMC Motion Front-End (fmc-mfe) aims at providing analog and digital environment for the control of up to 8-axis. More info at the Wiki page

The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function uses a 1ppm 20-Bit DAC (AD5791) as a reference and can be programmed as a differential voltage source. The card also includes 8 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.

The DAPHNE front end board is a piece of hardware that digitizes the output signal from one of the systems of the far detector in the DUNE experiment. For more information, see the wiki