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An FMC to test the correct mounting of FMC connectors on FMC carrier boards.

Software to support the FMC ADC 250M 16B 4CH mezzanine, including: configuration application and HDL firmware, with functionality for data acqusition. For use with FCS application. More info at the Wiki page

A Trigger/Timing Logic Unit to synchronize devices at beam test A successor to the AIDA(2020) TLU (https://ohwr.org/project/fmc-mtlu) This is an "umbrella" project with documentation, pointing to the projects with the hardware and firm(gate)ware

A level conversion board between TTL and 24V blocking levels in VME64x form factor. The project uses a rear transition module for connectivity and a front module with the active conversion and diagnostics electronics. More info at the Wiki page

The GBT-based Expandable Front-End (GEFE) is a multipurpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. More info at the Wiki page

The differential to single ended cable driver is an active electronics circuit that implements a high-current differential receiver, with optional attenuation (0dB, 6dB, 10dB and 12dB available), polarity inversion and ground lifting on input and output. More info at the Wiki page

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

The dual channel L band front-end consist of a FMC dual channel L band down-converter, preamplifiers and duplex filters. Each IQ down-converter has a wide adjustable bandwidth (>100 MHz), adjustable gain and two 250MHz 8 bits or 160 MHZ 12 bits or 105MHZ 14 bits multi-mode ADC's. The down-converter mode is switchable: single receiving frequency band for both channels, or dual frequency band: each channel has its own receiving frequency band. For GNSS its includes timing support, Other applications are radio astronomy and microwave digitizing back-end.

A VME rear transition module providing fibre-optic and electrical (RS485) inputs and outputs. Uses the CONV-TTL-RS485 as front-module. More info at the Wiki page

FmcAdc200k16b11cha is an 11 channel 200kSPS 16 bit ADC card in FMC (FPGA Mezzanine Card) standard. The input voltage range is settable to /-10V or/-5V. The input impedance is 1MOhm.

This project presents an FPGA architecture for the computation of visual attention based on the combination of a bottom-up saliency and a top-down task-dependent modulation streams. The bottom-up stream is deployed including optical flow, local energy, red-green and blue-yellow color opponencies, and different local orientation maps. The final saliency is modulated by two highlevel features: optical flow and disparity. The architecture include some feedback masks to adapt the weights of the features that are part of the bottom-up stream, depending on the specific target application. The target applications are ADAS (Advanced Driving Assistance Systems), video surveillance, robotics, etc...

Programmable attenuator of RF signals with very high voltage range (50 mV – 1000 V) for protecting digitizers against damage by high voltage signals. Four channels with SMA connectors; Three attenuation values: 0, -20, -40 dB; Bandwidth: DC – 2 GHz. VME form factor with I2C management bus. No VME-bus interface, only power supply used. More info at the Wiki page

pcie-fmc-soc-vdas is a PCIe carrier for a high pin count FPGA Mezzanine Card (VITA 57). The main component is a SOC chip used in cellular base stations that can do advanced processing. More info at the Wiki page

The Peak Position Detector is a 2 differential channel 10MSPS 16 bit ADC (AD7626) card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 41). Two general purpose 50MSPS 16-Bit DAC are implemented and can be programmed as a voltage source. The card also includes 6 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor.

wbgen2 is a tool for generating VHDL/Verilog cores which implement Wishbone bus slaves with certain registers, memory blocks, FIFOs and interrupts. The input is a C-like syntax file with an abstract description of what do we want to have in the slave. As a result, we get:

- Automatically allocated memory layout

- VHDL/Verilog code for the slave module

- C header files for driver development - Nice HTML documentation

Read the wbgen2-Documentation Get the latest version binaries https://www.ohwr.org/attachments/5659/wbgen2-bin.tar.bz2

A system to characterise large area silicon pad sensors with several hundred channels. It consists of two PCBs. One is an active switching 512-to-1 matrix. The second one is a passive probe card to contact the sensor. Software.

COM Express based PXIe system controller. COM Express Compact Pin-out type 6, 16-lane PCIe GEN3. PXIe trigger line on front-panel. More info at the Wiki page

An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.

More information on the wiki page The design is currently used only for the CERN RF-group purposes