This open-source 3DMASK offers a FFP2-level protection with the right filter material. It can be produced by anybody in possession of a 3D printer. More info at the Wiki page.

An implementation of a receiver for CERN's Beam Synchronous Timing (BST) on a SVEC.

RF over Ethernet, a protocol. Based on an extension of IEEE 1914.3 - IEEE Standard for Radio over Ethernet Encapsulations and Mappings. More info at the Wiki page

FMC LPC card with two High Voltage (HV) outputs and one Low Voltage (5-10V) output. Has mV voltage sensing and mA current sensing capabilities. More info at the Wiki page

High precision, ultra stable Oven Controlled Crystal Oscillator (OCXO) suitable for the Metrology purposes in a 19" format. Can be used to upgrade the performance of the SPEC7.

High-resolution frequency/phase-microstepper for timing laboratories. More info at the Wiki page

Zynq CarrIer for Timing sYstems based on radiofrequency over White Rabbit, aka CITY.

FMCprojects shows the FMC Mezzanine and Carrier boards that are developed in the Open Hardware Repository context. Furthermore it gives useful data helping you to design modules complying to this VITA 57.1 standard. This actually is not a hardware project, but is there to help you find your way in the FMC standard and shows you which FMC Mezzanines and Carriers are being developed in the context of the Open Hardware project.

OHR project where you can get help and guidelines about OHR. It's a support project for questions/feedback and bugs. More info at the Wiki page

A meta project used to discuss and present information about Open Hardware and related subjects. More info at the Wiki page More info about the CERN Open Hardware licence More info about the OHR.org site support

A Time to Digital Converter core for Spartan 6 FPGAs.

The FmcAdc1G8b2cha is a 2 channel 1GSPS 8 bit ADC card in FMC (FPGA Mezzanine Card, VITA 57.1) format using a Low Pin-Count (LPC) connector.

More info at the Wiki Page

FmcDIO5chTTLa is a 5-bit port digital IO card in FMC form-factor. Each single-bit port can be configured individually as input or output. The I/Os on LEMO 00 connectors are TTL compatible. Commercially available. More info at the Wiki page

An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page

Production and functional tests for fmc-dac-600m-12b-1cha-dds

The CUTE-WR-DP is the enhanced version of CUTE-WR with dual WR ports. You can use it as the normal WR node with one SFP port. CUTE-WR-DP can work in chain to support cascade topology. In future, CUTE-WR-DP could support dualport redundancy function for high reliable application. More info at the Wiki page

A White Rabbit Timing Receiver in AMC (Advanced Mezzanine Card, AdvancedMC) format. More info at the Wiki page

Project exploring the current limits of White Rabbit timing distribution and how to obtain the best possible jitter and Allan Deviation performance

FmcDIO10i8o is an I/O card in FMC form-factor. Its 10 inputs use fast differential comparators (propagation delay < 1 ns) with individual 8-bit DACs of minimum 1 MSPS output settling. The 8 outputs are TTL level. More info at the Wiki page

A White Rabbit Timing Receiver in PMC (PCI Mezzanine Card) format. More info at the Wiki page