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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA

This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification

Mock Turtle is an HDL core of a generic control system node, based on a deterministic multicore CPU architecture. Mock Turtle can use White Rabbit as the means of communication and synchronization in a distributed system. More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.