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  • FMC nanoFIP is an interface card for the WorldFIP network in an LPC FMC form-factor. More info at the Wiki page

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  • A VME rear transition module providing fibre-optic and electrical (RS485) inputs and outputs. Uses the CONV-TTL-RS485 as front-module. More info at the Wiki page

    Topics: VME RTM
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  • The GBT-based Expandable Front-End (GEFE) is a multipurpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. More info at the Wiki page

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  • The GSI Timing Starter Kit is a functional snapshot of the eventual FAIR timing system, which is under active development. It demonstrates real-time coordination of two front-end equipment controllers. The product consists of a data master (Linux PC) which coordinates events, a timing master which synchronizes clocks (White Rabbit switch), and two front-end equipment controllers (either SPECv4 or SCUv2).

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  • This project guides new users to start in the White Rabbit “World” with simple experiments. The starting kit uses two SPEC + FMC-DIO cards. Each node allows basic operations such as input timestamping or programmable output pulse generation. Additionally, specific software and gateware layers allow to use it as a standard network interface card implementing the White Rabbit technology functionalities.

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  • WorldFIP is a deterministic rad-tol fieldbus used at CERN's LHC for a variety of control systems. Cryogenics, Power Converters, Beam Instrumentation and other critical systems are using WorldFIP for the exchange of data between their sensors and actuators and the control and supervision level. With Alstom phasing out WorldFIP support in 2009, it was decided to insource this technology at CERN.

    The insourcing project has started with , a rad-tol FPGA that acts as an agent in the communication over the WorldFIP fieldbus.

    nanoFIP project details, specifications, design and users information

    In view of reorganizing the project, the nanoFIP project contains a copy of the CERNFIP wiki pages, Documents and Issues made on 24 March 2015

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  • The FmcAdc250M12b2cha is a 2 channel 250MSPS 12 bit ADC card in FMC (FPGA Mezzanine Card) format using an LPC connector. The gain can be set by software in three steps: /-50mV,/-0.5V, /-5V. An advanced offset circuit is used in the front-end design of the ADC board, and allows a voltage shift in the range of/- 5V that is independent on the chosen gain range.

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  • Libre-FDATool is a Python package aimed at helping in the analysis and design of HDL filters from high-level specifications. This Free/Libre Open Source software supports both VHDL and Verilog code generation and relies on a collection of Free scientific and EDA tools for providing advanced features -- simulation, graphics, debugging, etc.

    In order to overcome the problems often related with deploying open design toolchains from the ground up across different host environments, Libre-FDATool and the associated third-party tools are alternatively distributed in a customized GNU/Linux virtual machine image. This virtualized solution is ready to use right out of the box and can be easily deployed by only using free software in any mainstream Operating System (GNU/Linux, Windows, OS-X, Solaris).

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  • Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page

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  • Hardware design of Conv TTL Blocking. Includes schematics, PCB layout and manufacturing files. More info at the Wiki page

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  • USB-controlled data acquisition and instrument controller, 4 analog inputs, 2 analog outputs, 4 digital inputs and 4 digital outputs. Maximum sampling rate of 3000 samples per seconds in continuous stream mode. On-board averaging at 50000 samples per seconds max. Available in 3 versions:

    BNC connectors Terminal Block connections OEM Header

    More info at the Wiki page

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  • Projects / meta-spec

    GNU General Public License v3.0 only

    Yocto Project / OpenEmbedded meta layer supporting the use of the Simple PCIe Carrier (SPEC) in x86 and x86-64 embedded Linux hosts. It features:

    SPEC software (kernel, userspace, library, gateware) White Rabbit Interface Card support. White Rabbit Starting Kit demos. Getting started with the SPEC demos (python, gateware) Ready to go minimal and sato image recipes.
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  • The B-Train integrator is a 2 differential channel 2MSPS 18 bit ADC card in FMC (FPGA Mezzanine Card) format. It uses an LPC VITA57 connector. The gain can be set by hardware (default = 1). A gain & offset self-calibrating function is also implemented. This function uses a 1ppm 20-Bit DAC (AD5791) as a reference and can be programmed as a differential voltage source. The card also includes 8 input/output LVDS pairs and a 10-bit port digital IO where each single-bit port can be configured individually as input or output. The I/Os that are on micro-HDMI connectors are TTL or LVDS compatible.

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  • The Furnarius Rufus PCB Milling Machine is an open-source digital fabrication tool designed to lower the costs of prototyping and small scale manufacturing of scientific and educational instruments. More info at the Wiki page

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  • Projects / DCES-DTRHF-SER1CH-v1

    GNU General Public License v3.0 only

    Data centre environmental sensor - Dust, Temperature, Relative Humidity, Fan - Serial 1 channel - version 1. An environmental sensor for Data Centers that continuously measures airborne particle density in high airflow as well as temperature and relative humidity. It can control its fan speed if needed (PWM controlled fans) and monitors FAN rotational speed (tachometer equipped fans) for precise airflow control and monitoring. It is close to maintenance free and can be integrated in compact enclosures (for example tape drive tray or even an ATX PSU case...). More info at the Wiki page

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  • It is a simple, low-cost measurement device equipped with GPS, GPRS modem, keyboard, display and LiOn battery. It can be also supplied/charged via a USB connector. It is enclosed in a nice-looking Hammond enclosure. It also has 3 RJ50 connectors that enable connection of various types of sensors. Each sensor can be connected using UART, I2C, SPI, 1-wire or analog interface. The device connects with a remote server which is also part of the development. We want to use them at Warsaw University of Technology to build a distributed network of sensors.

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  • EPICS support for Wishbone peripherals: This project consist of a Generic EPICS IOC AsynDriver to support wishbone peripheral. It include the following features:

    Driver for X1052, Gennum, Etherbone WB master. Direct access to any register in the wishbone bus Auto-generation of EPICS Database file using wbgen2 Automatic real number convertion (2 complements, fixed point, signess) using .wb file Support for WR Core and other internal bus protocols (i2c, spi, etc.)

    More info at the Wiki page

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  • Fmc-adc-iso-400k18b4cha is a 4 channel 400kSps 18 bit ADC low pin count FPGA Mezzanine Card (VITA 57). The ground reference used for the analog inputs and the ADC is isolated from the ground reference of the FMC connector. Digital Isolators included allow the data transmission between two isolated areas. Voltage Bias between two grounds of up to 1kV can be applied, which is measured with a 100MOhm resistor connected between two grounds and an additional 10 bit ADC. Analog input voltage ranges: /-5V,/-10V. More info at the Wiki page

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  • This project presents an FPGA architecture for the computation of visual attention based on the combination of a bottom-up saliency and a top-down task-dependent modulation streams. The bottom-up stream is deployed including optical flow, local energy, red-green and blue-yellow color opponencies, and different local orientation maps. The final saliency is modulated by two highlevel features: optical flow and disparity. The architecture include some feedback masks to adapt the weights of the features that are part of the bottom-up stream, depending on the specific target application. The target applications are ADAS (Advanced Driving Assistance Systems), video surveillance, robotics, etc...

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