Explore projects
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Introductory SoC course with reference designs based on the Xilinx Vitis Unified Software Development Platform and targeted to the Xilinx Zynq UltraScale+ MPSoC. More info at the Wiki page
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OpenBreath / Open Breath PEP Whistle
CERN Open Hardware Licence Version 2 - Strongly ReciprocalUpdated -
OpenBreath / Open Breath Lung Ventilator
CERN Open Hardware Licence Version 2 - Strongly ReciprocalOpen Breath lung ventilator. It is developed to be low-cost, scalable and easily manufactured. It can be used in Pressure and Volume Control, SIMV+PS and CPAP functions. More info at the Wiki page
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Projects / White Rabbit Switch - Software
GNU General Public License v2.0 or laterDevelopment of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor. More info at the Wiki page
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DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.
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GTS is a tool which takes a binary for a given microprocessor (initially an LM32) and gives information about worst-case execution time.
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A card used in CERN's Linac 3 for the control of the electromagnetic field inside RF accelerating cavities.
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An FMC for clock & data recovery from optical sources.
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A Virtex6-based optical link interface AMC equipped with SFP+ and FMC sockets
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A High Pin Count FMC carrier in VXS format with two Virtex 5 FPGAs plus a DSP on board.
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An FMC to test the correct mounting of FMC connectors on FMC carrier boards.
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A three-channel TTL to NIM (Nuclear Instrumentation Module) level conversion board in VME form factor. More info at the Wiki page
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A transparent Wishbone bridge between two FPGAs using high-speed serial links. This project is on hold.* More info at the Wiki page
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A converter between USB/Ethernet and WorldFIP, allowing the bus arbitration and control of a WorldFIP fieldbus segment from a USB or Ethernet-equipped computer.
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Projects / AIDA-2020 TLU
OtherA Trigger/Timing Logic Unit designed for use with High Energy Physics beam-tests. Provides a simple and flexible interface for fast timing and triggering signals at the AIDA pixel sensor beam-telescope. Connects to a FPGA carrier card via a FMC connector.
( N.B. Use the sub-project Git repositories, not the top level repository )
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An HPC FMC with 4 Digital to Analog Converter channels working at 250 MS/s with 16-bit resolution.
More information on the wiki page The design is currently used only for the CERN RF-group purposesUpdated -