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This is a PCB-design + Arduino firmware for an Ethernet-controlled 1:8 RF-multiplexer. It allows selecting as output one of eight input-channels, as commonly used e.g. in timing-laboratories when one wants to measure many RF-sources (clock outputs like 1PPS or 10MHz) with a single instrument (frequency or time-interval counter). The design is for two independent MUX-boards to fit in a 1U 19” rack enclosure. For more information, see the wiki
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Projects / powerlink
BSD 3-Clause "New" or "Revised" LicensePowerlink Industrial Ethernet stack. It runs on top of the Hydra rad-tol SoC project. More info at the Wiki page
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Projects / White Rabbit Switch - Software
GNU General Public License v2.0 or laterDevelopment of software for the White Rabbit switch, and in particular the embedded Linux system running in the ARM9 processor. More info at the Wiki page
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An FPGA Mezzanine Card (FMC) with a Time to Digital Converter chip to perform one-shot sub-nanosecond time interval measurements. Commercially available. More info at the Wiki page
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Projects / Respir-OS
GNU General Public License v3.0 or laterOpen design and implementation of a low-cost ventilator for COVID-19 patients. More info at the Wiki page
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A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.
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HoloBlade is an open-hardware driver-stack for Spatial Light Modulators (SLMs). Its primary application is for holographic displays and may be used in applied optics research fields as telecommunications, astronomy, microscopy and optical computing.
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A 4-lane PCIe carrier for a low pin count FPGA Mezzanine Card (VITA 57). SPEC carrier based with a larger FPGA. Commercially available. More info at the Wiki page
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The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Software.
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The TimIQ system is an IQ modulator allowing to phase shift a radio frequency clock with a resolution of 40 fs and an accuracy of 8 ps. Hardware.
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19"-rack mounted module which connects 20 single-ended K-type or N-type thermocouple channels with zQSFP+ to samb-temp-thcpl-fmc. Used in SAMbuCa project. More info at the Wiki page
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FMC thermocouple card interfacing with zQSFP+ to samc-temp-thcpl-20ch which connects 20 single-ended K-type or N-type thermocouple channels. Used in SAMbuCa project. More info at the Wiki page
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A WR compliant Network Interface Core (WR-NIC) for 1G and 10G Ethernet communication. More info at the Wiki page
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Tester board to test PXIe processor modules. Two variants: slot 2 and slot 10 (system timing slot). More info at the Wiki page
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Study of the “Open Hardware Initiative” at CERN with a focus on the technologies of participation that were mobilized to assemble critical infrastructure for basic research in high energy physics.
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The FMC Motion Front-End (fmc-mfe) aims at providing analog and digital environment for the control of up to 8-axis. More info at the Wiki page
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A software suite written in Python to help with production tests of PCBs. AKA PTS.
%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.
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FPGA Firmware ( "Gateware" ) for AIDA-2020 TLU and AIDA mini-TLU
Uses "IPBus Build" ( ipbb )
Build instructions at Instructions here
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E-bone first aims at interfacing an FPGA based PCIe Endpoint core to a collection of other cores. The E-bone release contains a number of general purpose cores within that scope. E-bone specifications cater for both a Control Interconnect and a Fast Transmitter. The Control Interconnect defines a 32 bit wide interconnection between a number of masters and slaves. The Fast Transmitter is a one way path (up to 256 bit wide) aiming at dumping large data sets to the root complex. E-bone is nevertheless not restricted to PCIe interfacing and may be used for developing sub-systems in others environments.
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