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Libre-FDATool is a Python package aimed at helping in the analysis and design of HDL filters from high-level specifications. This Free/Libre Open Source software supports both VHDL and Verilog code generation and relies on a collection of Free scientific and EDA tools for providing advanced features -- simulation, graphics, debugging, etc.

In order to overcome the problems often related with deploying open design toolchains from the ground up across different host environments, Libre-FDATool and the associated third-party tools are alternatively distributed in a customized GNU/Linux virtual machine image. This virtualized solution is ready to use right out of the box and can be easily deployed by only using free software in any mainstream Operating System (GNU/Linux, Windows, OS-X, Solaris).

Data centre environmental sensor - Dust, Temperature, Relative Humidity, Fan - Serial 1 channel - version 1. An environmental sensor for Data Centers that continuously measures airborne particle density in high airflow as well as temperature and relative humidity. It can control its fan speed if needed (PWM controlled fans) and monitors FAN rotational speed (tachometer equipped fans) for precise airflow control and monitoring. It is close to maintenance free and can be integrated in compact enclosures (for example tape drive tray or even an ATX PSU case...). More info at the Wiki page

Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page

A software suite written in Python to help with production tests of PCBs. AKA PTS.

%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.

More info at the Wiki page

A collection of platform-independent cores such as memories, synchronizer circuits and Wishbone cores.

More info at the Wiki page

A cute-wr is a compact WR-node implementation with minimum components required. The initial design is derived from SPEC, but would work in an opposite manner as a FMC wr-nic, providing 2 DIO channels, external CLK input, EEPROM, JTAG, RS232, and expandable IOs through FMC connector. The gateware and software of cute-wr would also keep maximum compatibility with SPEC. Project is obsolete. See cute-wr-dp for a similar board.

Detailed documentation on how to get ready to work with the Simple PCI Express Carrier, including hardware deployment instructions, full required toolchain setup and and a collection of step-by-step demonstrative tutorials.

Software for Beam Position Monitor, including digital signal processing chains, data acquisition engines, ADC and analog front-end peripherals control/monitoring, timing and control system interface.

A software suite written in Python to help with production tests of PCBs. AKA PTS.

%(red)This pts-base project is used to re-organise the current pts project In the future this project will replace the existing pts project.

More info at the Wiki page

DDR3 controller with two pipelined Wishbone slave ports. It is based on the Spartan6 hardware core and a management core generated by Xilinx CoreGen.

ADC testing procedures and software. More info at the Wiki page

The FMC bus abstraction implements a Linux kernel bus named fmc. This allows to deal with FMC mezzanines in a carrier-independent way

Software to support the FMC ADC 400k 18b 4cha iso mezzanine, including Linux device driver, library and test program.

A software framework for Linux device drivers aimed at supporting controls and data acquisition hardware. ZIO supports sub-nanosecond timestamps, block-oriented input and output and transport of meta-data with the data samples. Users can change the buffer type and trigger type associated with a device at run time, and all of devices, triggers and buffers are easily implemented as add-on modules.

The PF_ZIO implementation, currently in beta status, implements a network interface to the ZIO transport, which allows each I/O channel to generate or receive network frames. Applications see the network of devices and can talk with several of them from the same socket. We support SOCK_STREAM, SOCK_DGRAM and SOCK_RAW.

Host-side software support for the fine delay FMC on the SPEC and SVEC FMC carriers.

More details in the project wiki

This project defines data structures, to be embedded in the FPGA memory address space, to enumerate the devices that have been synthetized in the current design. The same structure is also used as a simple flash file system. AKA Self-Describing Bus (SDB) Specification for Logic Cores. The layout is simple enough to be parsed both by the host and by the internal soft-core, if any.

The documentation is public, and related code is GNU GPL licensed.

Production and functional tests for FMC ADC 100M 14b 4cha.

CompactRIO module with White Rabbit functionality. LabVIEW support, front-panel connector with 10 I/O lines.

More info at the Wiki page

SDB (Self-describing Bus) allows to enumerate the cores that are live in the current FPGA binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. The project provides the software support and the specification. More info at the Wiki page