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Projects / Euro ADC 65M 14b 40cha hw PUMA-hw
CERN Open Hardware Licence v1.2Updated -
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated