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Distribution of clock signals over a White Rabbit network. It uses an PLL with a numerically controlled (DDS) oscillator to extract the characteristics of a signal that in turn are distributed over a White Rabbit network to receiving nodes with a DAC that regenerate exactly the same signal in phase. More info at the Wiki page
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The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA
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Mathieu Saccani / VME64x core - msaccani
GNU Lesser General Public License v2.1 onlyA VHDL core for a VME64x slave. The other side behaves like a Wishbone master.
More info at the Wiki pageUpdated -
A collection of cores needed in the White Rabbit node and switch. Includes White Rabbit PTP Core (WRPC).
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This project contains gateware for the Distributed IO Tier demonstrator according to the CERN Warm Interlocks specification
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Multi-channel Time Interval Counter and fine delay generator. Housed in a 19" module. Research project. More info at the Wiki page
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hdl-core-lib / vme64x-core
GNU Lesser General Public License v2.1 onlyREAD-ONLY PROJECT TO PRESERVE EXISTING REMOTE URLS
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