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euro-adc-65m-14b-40cha-gw
Commit 8812fd0f authored by Dave Newbold's avatar Dave Newbold
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Removing inter-channel links

parent 3f1de9cc
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Showing with 1 addition and 12 deletions
components/solid/firmware/hdl/sc_chan.vhd
View file @ 8812fd0f
...@@ -36,8 +36,6 @@ entity sc_chan is ...@@ -36,8 +36,6 @@ entity sc_chan is
clk280: in std_logic; clk280: in std_logic;
d_p: in std_logic; d_p: in std_logic;
d_n: in std_logic; d_n: in std_logic;
d_test: in std_logic_vector(13 downto 0);
q_test: out std_logic_vector(13 downto 0);
sync_ctrl: in std_logic_vector(3 downto 0); sync_ctrl: in std_logic_vector(3 downto 0);
zs_sel: in std_logic_vector(1 downto 0); zs_sel: in std_logic_vector(1 downto 0);
sctr: in std_logic_vector(47 downto 0); sctr: in std_logic_vector(47 downto 0);
...@@ -152,7 +150,7 @@ begin ...@@ -152,7 +150,7 @@ begin
with ctrl_src select d_buf <= with ctrl_src select d_buf <=
d_in_i when "00", d_in_i when "00",
d_test when "01", (others => '0') when "01",
"00" & sctr_p when "10", "00" & sctr_p when "10",
fake when others; fake when others;
...@@ -202,7 +200,6 @@ begin ...@@ -202,7 +200,6 @@ begin
nzs_en => nzs_en, nzs_en => nzs_en,
cap_full => cap_full, cap_full => cap_full,
zs_thresh => zs_thresh, zs_thresh => zs_thresh,
q_test => q_test,
zs_en => zs_en, zs_en => zs_en,
buf_full => buf_full, buf_full => buf_full,
keep => keep_i, keep => keep_i,
......
components/solid/firmware/hdl/sc_chan_buf.vhd
View file @ 8812fd0f
...@@ -28,7 +28,6 @@ entity sc_chan_buf is ...@@ -28,7 +28,6 @@ entity sc_chan_buf is
nzs_en: in std_logic; -- enable nzs buffer; clk40 dom nzs_en: in std_logic; -- enable nzs buffer; clk40 dom
cap_full: out std_logic; cap_full: out std_logic;
zs_thresh: in std_logic_vector(13 downto 0); -- ZS threshold; clk40 dom zs_thresh: in std_logic_vector(13 downto 0); -- ZS threshold; clk40 dom
q_test: out std_logic_vector(13 downto 0); -- test data output to adjacent channel; clk40 dom
zs_en: in std_logic; -- enable zs buffer; clk40 dom zs_en: in std_logic; -- enable zs buffer; clk40 dom
buf_full: out std_logic; -- buffer err flag; clk40 dom buf_full: out std_logic; -- buffer err flag; clk40 dom
keep: in std_logic; -- block transfer cmd; clk40 dom keep: in std_logic; -- block transfer cmd; clk40 dom
...@@ -143,8 +142,6 @@ begin ...@@ -143,8 +142,6 @@ begin
cap_full <= cap_done; cap_full <= cap_done;
-- Zero suppression -- Zero suppression
q_test <= q_ram(13 downto 0);
z0 <= '1' when unsigned(q_ram(13 downto 0)) < unsigned(zs_thresh) and q_ram(15) = '0' else '0'; z0 <= '1' when unsigned(q_ram(13 downto 0)) < unsigned(zs_thresh) and q_ram(15) = '0' else '0';
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ 8812fd0f
...@@ -59,8 +59,6 @@ architecture rtl of sc_channels is ...@@ -59,8 +59,6 @@ architecture rtl of sc_channels is
signal chan_q: chan_q_t; signal chan_q: chan_q_t;
signal chan_q_blkend, chan_q_empty, chan_ren: std_logic_vector(N_CHAN - 1 downto 0); signal chan_q_blkend, chan_q_empty, chan_ren: std_logic_vector(N_CHAN - 1 downto 0);
signal sel: integer range N_CHAN - 1 downto 0 := 0; signal sel: integer range N_CHAN - 1 downto 0 := 0;
type chan_q_test_t is array(N_CHAN - 1 downto 0) of std_logic_vector(13 downto 0);
signal q_test: chan_q_test_t;
begin begin
...@@ -86,7 +84,6 @@ begin ...@@ -86,7 +84,6 @@ begin
cgen: for i in N_CHAN - 1 downto 0 generate cgen: for i in N_CHAN - 1 downto 0 generate
signal ren_loc: std_logic; signal ren_loc: std_logic;
constant p: integer := i + 1 - 2 * (i mod 2);
signal ltrig: std_logic_vector(N_CHAN_TRG - 1 downto 0); signal ltrig: std_logic_vector(N_CHAN_TRG - 1 downto 0);
begin begin
...@@ -108,8 +105,6 @@ begin ...@@ -108,8 +105,6 @@ begin
clk280 => clk280, clk280 => clk280,
d_p => d_p(i), d_p => d_p(i),
d_n => d_n(i), d_n => d_n(i),
d_test => q_test(p),
q_test => q_test(i),
sync_ctrl => sync_ctrl, sync_ctrl => sync_ctrl,
zs_sel => zs_sel, zs_sel => zs_sel,
sctr => sctr, sctr => sctr,
......
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