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euro-adc-65m-14b-40cha-gw
Commit 706e11fa authored by Daniel Saunders's avatar Daniel Saunders
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Merge branch 'master' of bitbucket.org:solidexperiment/solid_firmware

parents eaafd022 b745568a
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Showing with 19 additions and 35 deletions
boards/pc051b/base_fw/synth/firmware/hdl/top_pc051b.vhd
View file @ 706e11fa
......@@ -18,7 +18,7 @@ entity top is port(
eth_tx_p: out std_logic; -- Ethernet MGT output
eth_tx_n: out std_logic;
leds: out std_logic_vector(1 downto 0); -- TE712 LEDs
leds_c: out std_logic_vector(2 downto 0); -- carrier LEDs
led: out std_logic; -- carrier LEDs
addr: in std_logic_vector(7 downto 0); -- carrier switches
sel: out std_logic_vector(4 downto 0); -- bus select lines to CPLD
i2c_scl: out std_logic; -- I2C bus via CPLD
......@@ -96,7 +96,7 @@ begin
nuke => nuke,
soft_rst => soft_rst,
stealth_mode => stealth_mode,
userleds => leds_c,
userled => led,
addr => addrn,
sel => sel,
i2c_scl => i2c_scl,
......
boards/pc051b/base_fw/synth/firmware/ucf/pc051b.tcl
View file @ 706e11fa
......@@ -45,11 +45,9 @@ set_property PACKAGE_PIN U22 [get_ports {leds[1]}]
false_path {leds[*]} eth_refclk
# Bank 14, 3V3
set_property IOSTANDARD LVCMOS33 [get_ports {leds_c[*]}]
set_property PACKAGE_PIN W19 [get_ports {leds_c[0]}]
set_property PACKAGE_PIN Y18 [get_ports {leds_c[1]}]
set_property PACKAGE_PIN W20 [get_ports {leds_c[2]}]
false_path {leds_c[*]} eth_refclk
set_property IOSTANDARD LVCMOS33 [get_ports led]
set_property PACKAGE_PIN W20 [get_ports led]
false_path led eth_refclk
# Bank 14, 3V3
set_property IOSTANDARD LVCMOS33 [get_ports {addr[*]}]
......
components/solid/firmware/hdl/ipbus_decode_sc_daq.vhd
View file @ 706e11fa
......@@ -17,7 +17,7 @@ package ipbus_decode_sc_daq is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_daq(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Thu Jun 15 20:45:58 2017
-- START automatically generated VHDL the Thu Oct 19 13:25:12 2017
constant N_SLV_CHAN: integer := 0;
constant N_SLV_TIMING: integer := 1;
constant N_SLV_FAKE: integer := 2;
......@@ -37,11 +37,11 @@ package body ipbus_decode_sc_daq is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Thu Jun 15 20:45:58 2017
-- START automatically generated VHDL the Thu Oct 19 13:25:12 2017
if std_match(addr, "-------------------------000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000000 / mask 0x00000070
elsif std_match(addr, "-------------------------0010---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000010 / mask 0x00000078
elsif std_match(addr, "-------------------------001----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000010 / mask 0x00000070
elsif std_match(addr, "-------------------------0100---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_FAKE, IPBUS_SEL_WIDTH)); -- fake / base 0x00000020 / mask 0x00000078
elsif std_match(addr, "-------------------------0101---") then
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ 706e11fa
......@@ -26,7 +26,7 @@ entity sc_daq is
sync_in: in std_logic;
trig_in: in std_logic;
trig_out: out std_logic;
led_out: out std_logic_vector(2 downto 0);
led_out: out std_logic;
chan: in std_logic_vector(7 downto 0);
chan_err: out std_logic;
d_p: in std_logic_vector(N_CHAN - 1 downto 0);
......@@ -93,7 +93,7 @@ begin
clk280 => clk280,
sync_in => sync_in,
trig_in => trig_in,
led => led_out(0),
led => led_out,
sctr => sctr,
chan_sync_ctrl => sync_ctrl,
trig_en => trig_en,
......@@ -244,18 +244,5 @@ begin
empty => ro_empty,
ren => ro_ren
);
-- LED
stretch: entity work.led_stretcher
generic map(
WIDTH => 2
)
port map(
clk => clk125,
d(0) => link_d_valid,
d(1) => link_ok,
q => led_out(2 downto 1)
);
end rtl;
components/solid/firmware/hdl/sc_timing.vhd
View file @ 706e11fa
......@@ -159,6 +159,7 @@ begin
end process;
io_err <= '1';
led <= not (wait_sync or sync_err);
-- Sample counter
......@@ -166,7 +167,7 @@ begin
begin
if rising_edge(clk40_i) then
if rst40_i = '1' or sync_f = '1' then
sctr_i <= (others => '0');
sctr_i <= X"000000000001";
else
sctr_i <= sctr_i + 1;
end if;
......@@ -177,7 +178,6 @@ begin
end process;
sctr <= std_logic_vector(sctr_i);
led <= sctr_i(LED_BLK_RADIX + BLK_RADIX - 1) and not (wait_sync or sync_err);
-- Random number gen
......
projects/64ch/firmware/hdl/payload.vhd
View file @ 706e11fa
......@@ -27,7 +27,7 @@ entity payload is
nuke: out std_logic;
soft_rst: out std_logic;
stealth_mode: out std_logic;
userleds: out std_logic_vector(2 downto 0);
userled: out std_logic;
addr: in std_logic_vector(7 downto 0);
sel: out std_logic_vector(4 downto 0);
i2c_scl: out std_logic; -- I2C bus via CPLD
......@@ -60,7 +60,7 @@ architecture rtl of payload is
signal ctrl_rst_mmcm, locked, idelayctrl_rdy, ctrl_rst_idelayctrl , ctrl_stealth_mode: std_logic;
signal ctrl_chan: std_logic_vector(7 downto 0);
signal chan_err: std_logic;
signal daq_leds: std_logic_vector(2 downto 0);
signal daq_led: std_logic;
begin
......@@ -107,7 +107,7 @@ begin
sel <= ctrl(0)(28 downto 24);
stealth_mode <= ctrl_stealth_mode;
userleds <= daq_leds when ctrl_stealth_mode = '0' else (others => '0');
userled <= daq_led and not ctrl_stealth_mode;
-- Required for timing alignment at inputs
......@@ -154,7 +154,7 @@ begin
sync_in => sync_in,
trig_in => trig_in,
trig_out => trig_out,
led_out => daq_leds,
led_out => daq_led,
chan => ctrl_chan,
chan_err => chan_err,
d_p => adc_d_p,
......
projects/64ch/firmware/hdl/top_decl.vhd
View file @ 706e11fa
......@@ -16,7 +16,6 @@ package top_decl is
constant N_CHAN: integer := 64;
constant BLK_RADIX: integer := 8; -- 256 sample blocks
constant SUPERBLK_RADIX: integer := 16; -- Superblock is 64k blocks
constant LED_BLK_RADIX: integer := 18; -- Divisor for blocks-per-led-flash
constant BUF_RADIX: integer := 11; -- One BRAM for NZS / ZS buffer
constant NZS_BLKS: integer := 2; -- Reserve two blocks of space for NZS buffer
constant ZS_BLKS: integer := 2; -- Time window for ZS buffer
......
projects/8ch/firmware/hdl/payload.vhd
View file @ 706e11fa
......@@ -123,7 +123,7 @@ begin
ctrl_board_id <= ctrl(0)(23 downto 16);
stealth_mode <= ctrl_stealth_mode;
userleds <= '0' & daq_leds when ctrl_stealth_mode = '0' else (others => '0');
userleds <= "0000" & daq_led when ctrl_stealth_mode = '0' else (others => '0');
-- Required for timing alignment at inputs
......@@ -210,7 +210,7 @@ begin
sync_in => sync_in,
trig_in => trig_in,
trig_out => trig_out,
led_out => daq_leds(2 downto 0),
led_out => daq_leds(2),
chan => ctrl_chan,
chan_err => chan_err,
d_p => adc_d_p,
......
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