Commit 5e46c47f authored by Dave Newbold's avatar Dave Newbold

Addrtab update

parent 10663d3a
......@@ -17,7 +17,7 @@ package ipbus_decode_top_sim is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_top_sim(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Mon Jun 5 23:01:57 2017
-- START automatically generated VHDL the Tue Jun 6 13:22:51 2017
constant N_SLV_CSR: integer := 0;
constant N_SLV_CHAN: integer := 1;
constant N_SLV_TIMING: integer := 2;
......@@ -37,11 +37,11 @@ package body ipbus_decode_top_sim is
variable sel: ipbus_sel_t;
begin
-- START automatically generated VHDL the Mon Jun 5 23:01:57 2017
-- START automatically generated VHDL the Tue Jun 6 13:22:51 2017
if std_match(addr, "------------------------0000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x000000f0
elsif std_match(addr, "------------------------0000----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000008 / mask 0x000000f0
elsif std_match(addr, "------------------------0001----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN, IPBUS_SEL_WIDTH)); -- chan / base 0x00000010 / mask 0x000000f0
elsif std_match(addr, "------------------------0100----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_TIMING, IPBUS_SEL_WIDTH)); -- timing / base 0x00000040 / mask 0x000000f0
elsif std_match(addr, "------------------------0101----") then
......
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