Skip to content

E
euro-adc-65m-14b-40cha-gw
Commit 10663d3a authored by Dave Newbold's avatar Dave Newbold
Browse files
Options

Address table update; redundant signal removal

parent 8f29794b
Hide whitespace changes
Inline Side-by-side
Showing with 2 additions and 14 deletions
components/solid/firmware/hdl/sc_daq.vhd
View file @ 10663d3a
......@@ -58,7 +58,7 @@ architecture rtl of sc_daq is
signal link_d_valid, link_q_valid, link_ack: std_logic;
signal ro_chan: std_logic_vector(7 downto 0);
signal ro_d, trig_d: std_logic_vector(31 downto 0);
signal ro_blkend, ro_empty, ro_ren, en_ro, trig_sync, trig_blkend, trig_we, trig_roc_veto: std_logic;
signal ro_blkend, ro_empty, ro_ren, trig_sync, trig_blkend, trig_we, trig_roc_veto: std_logic;
signal rand: std_logic_vector(31 downto 0);
begin
......
projects/8ch/addr_table/top_sim.xml
View file @ 10663d3a
<node id="TOP">
<node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x8" module="file://sc_chan.xml"/>
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
......
projects/8ch/firmware/sim_hdl/payload_sim.vhd
View file @ 10663d3a
......@@ -36,18 +36,6 @@ architecture rtl of payload_sim is
signal ctrl_rst_mmcm, locked, idelayctrl_rdy, ctrl_rst_idelayctrl: std_logic;
signal ctrl_chan: std_logic_vector(7 downto 0);
signal ctrl_board_id: std_logic_vector(7 downto 0);
signal sync_ctrl: std_logic_vector(3 downto 0);
signal adc_d: std_logic_vector(N_CHAN - 1 downto 0);
signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en, chan_err: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
signal link_d_valid, link_q_valid, link_ack: std_logic;
signal ro_chan: std_logic_vector(7 downto 0);
signal ro_d, trig_d: std_logic_vector(31 downto 0);
signal ro_blkend, ro_empty, ro_ren, en_ro, trig_sync, trig_blkend, trig_we, trig_roc_veto: std_logic;
signal rand: std_logic_vector(31 downto 0);
begin
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment