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euro-adc-65m-14b-40cha-gw
Commit 45238368 authored by Dave Newbold's avatar Dave Newbold
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Adding fake data generator

parent 0e13ce4b
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Showing with 152 additions and 7 deletions
components/solid/addr_table/sc_fake.xml 0 → 100644
View file @ 45238368
<node id="fake" description="Fake data generator" fwinfo="endpoint">
<node id="ctrl" address="0x0" description="fake data ctrl" fwinfo="endpoint;width=0">
<node id="en" mask="0x1"/>
<node id="mode" mask="0x2"/>
<node id="force" mask="0x4"/>
<node id="samp_lock" mask="0x8"/>
</node>
<node id="params" address="0x0" description="fake data params" fwinfo="endpoint;width=1">
<node id="freq" address="0x0">
<node id="freq_div" mask="0xf"/>
<node id="n" mask="0xff00"/>
<node id="gap" mask="0xff0000"/>
<node id="samp" mask="0xff000000"/>
</node>
<node id="size" address="0x1">
<node id="ampl" mask="0x3ff"/>
<node id="ped" mask="0x3ff0000"/>
</node>
</node>
components/solid/firmware/cfg/sc_fake.dep 0 → 100644
View file @ 45238368
src sc_fake.vhd
addrtab -t sc_fake.xml
src ipbus_decode_sc_fake.vhd
src -c ipbus-firmware:components/ipbus_slaves ipbus_ctrlreg_v.vhd
include -c ipbus-firmware:components/ipbus_slaves syncreg_v.dep
src -c ipbus-firmware:components/ipbus_slaves ipbus_reg_types.vhd
components/solid/firmware/hdl/sc_daq.vhd
View file @ 45238368
......@@ -97,8 +97,11 @@ begin
clk => ipb_clk,
rst => ipb_rst,
ipb_in => ipb_in_fake,
ipb_out => ipb_out_fake,
ipb_out => ipb_out_fake,
clk40 => clk40_i,
rst40 => rst40_i,
rand => rand,
sctr => sctr(7 downto 0),
fake => fake
);
......
components/solid/firmware/hdl/sc_fake.vhd
View file @ 45238368
......@@ -10,6 +10,7 @@ use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.ipbus.all;
use work.ipbus_decode_sc_fake.all;
use work.ipbus_reg_types.all;
entity sc_fake is
......@@ -18,7 +19,10 @@ entity sc_fake is
rst: in std_logic;
ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus;
clk40: in std_logic;
rst40: in std_logic;
rand: in std_logic_vector(31 downto 0);
sctr: in std_logic_vector(7 downto 0);
fake: out std_logic_vector(13 downto 0)
);
......@@ -26,10 +30,123 @@ end sc_fake
architecture rtl of sc_fake is
signal ipbw: ipb_wbus_array(N_SLAVES - 1 downto 0);
signal ipbr: ipb_rbus_array(N_SLAVES - 1 downto 0);
signal ctrl: ipb_reg_v(0 downto 0);
signal stb: std_logic_vector(0 downto 0);
signal ctrl_en, ctrl_mode, ctrl_force, ctrl_samp_lock: std_logic;
signal params: ipb_reg_v(1 downto 0);
signal params_freq_div: std_logic_vector(3 downto 0);
signal params_n, params_gap, params_samp: std_logic_vector(7 downto 0);
signal params_ampl, params_ped: std_logic_vector(13 downto 0);
signal mask: std_logic_vector(15 downto 0);
signal pulse: std_logic_vector(13 downto 0);
signal p, go, samp, pend, act, done: std_logic;
signal pcnt, gcnt: unsigned(7 downto 0);
begin
ipb_out <= IPB_RBUS_NULL;
-- ipbus address decode
fabric: entity work.ipbus_fabric_sel
generic map(
NSLV => N_SLAVES,
SEL_WIDTH => IPBUS_SEL_WIDTH
)
port map(
ipb_in => ipb_in,
ipb_out => ipb_out,
sel => ipbus_sel_sc_fake(ipb_in.ipb_addr),
ipb_to_slaves => ipbw,
ipb_from_slaves => ipbr
);
-- Ctrl
csr: entity work.ipbus_syncreg_v
generic map(
N_CTRL => 1
)
port map(
clk => clk,
rst => rst,
ipb_in => ipbw(N_SLV_CTRL),
ipb_out => ipbr(N_SLV_CTRL),
slv_clk => clk40,
q => ctrl,
stb => stb
);
ctrl_en <= ctrl(0)(0);
ctrl_mode <= ctrl(0)(1);
ctrl_force <= ctrl(0)(2) and stb(0);
ctrl_samp_lock <= ctrl(0)(3);
-- Parameters
csr: entity work.ipbus_ctrlreg_v
generic map(
N_CTRL => 2
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipbw(N_SLV_PARAMS),
ipbus_out => ipbr(N_SLV_PARAMS),
q => params
);
params_freq_div <= params(0)(3 downto 0);
params_n <= params(0)(15 downto 8);
params_gap <= params(0)(23 downto 16);
params_samp <= params(0)(31 downto 24);
params_ampl <= params(1)(13 downto 0);
params_ped <= params(1)(29 downto 16);
-- Trigger
process(params_freq_div)
begin
for i in mask'range loop
if i > to_integer(unsigned(params_freq_div)) then
mask(i) <= '0';
else
mask(i) <= '1';
end if;
end loop;
end process;
go <= '1' when ctrl_force = '1' or (or_reduce(mask and rand(27 downto 12)) = '0' and or_reduce(rand(11 downto 0)) = '0') else '0';
samp <= '1' when ctrl_samp_lock = '0' or sctr = params_samp else '0';
pend <= (pend or (go and not act)) and not (rst40 or act) when rising_edge(clk40);
act <= (act or (pend and samp)) and not (rst40 or done) when rising_edge(clk40);
-- Pulse generator
process(clk40)
begin
if rising_edge(clk40) then
if rst40 = '1' or done = '1' then
pcnt <= (others => '0');
gcnt <= (others => '0');
elsif act = '1' then
if gcnt = 0 then
gcnt <= unsigned(params_gap);
p <= '1';
pcnt <= pcnt + 1;
else
gcnt <= gcnt - 1;
p <= '0';
end if;
end if;
end if;
end process;
done <= '1' when pcnt = params_n else '0';
-- Output
fake <= rand(13 downto 0);
pulse <= std_logic_vector(unsigned(params_ped) + unsigned(params_ampl)) when p = '1' else params_ped;
fake <= rand(13 downto 0) when mode = '0' else pulse;
end rtl;
projects/64ch/addr_table/top.xml
View file @ 45238368
......@@ -3,7 +3,7 @@
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="io" address="0x20" module="file://sc_io_64chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
......
projects/64ch/addr_table/top_sim.xml
View file @ 45238368
......@@ -2,7 +2,7 @@
<node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x8" module="file://sc_chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
......
projects/8ch/addr_table/top.xml
View file @ 45238368
......@@ -3,7 +3,7 @@
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="io" address="0x20" module="file://sc_io.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
......
projects/8ch/addr_table/top_sim.xml
View file @ 45238368
......@@ -2,7 +2,7 @@
<node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x8" module="file://sc_chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
......
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