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euro-adc-65m-14b-40cha-gw
Commit 0e13ce4b authored by Dave Newbold's avatar Dave Newbold
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Adding skeleton fake data generator

parent a998ebab
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Showing with 68 additions and 15 deletions
components/solid/firmware/cfg/sc_daq.dep
View file @ 0e13ce4b
src sc_daq.vhd
src sc_fake.vhd
include sc_timing.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/cfg/sc_daq_sim.dep
View file @ 0e13ce4b
src sc_daq.vhd
src sc_fake.vhd
include sc_timing_sim.dep sc_chan.dep sc_trig.dep sc_trig_link.dep sc_roc.dep
src -c ipbus-firmware:components/ipbus_core ipbus_package.vhd
components/solid/firmware/hdl/sc_chan.vhd
View file @ 0e13ce4b
......@@ -3,7 +3,7 @@
-- All the stuff belonging to one input channel
--
-- ctrl_mode: 0 normal; 1 playback; 2 capture; 3 reserved
-- ctrl_src: 0 external; 1 playback buffer; 2 counter; 3 random data
-- ctrl_src: 0 external; 1 playback buffer; 2 counter; 3 fake data
--
-- Dave Newbold, February 2016
......@@ -40,7 +40,7 @@ entity sc_chan is
q_test: out std_logic_vector(13 downto 0);
sync_ctrl: in std_logic_vector(3 downto 0);
sctr: in std_logic_vector(13 downto 0);
rand: in std_logic_vector(13 downto 0);
fake: in std_logic_vector(13 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
keep: in std_logic;
......@@ -143,7 +143,7 @@ begin
d_in_i when "00",
d_test when "01",
sctr when "10",
rand when others;
fake when others;
-- Channel status
......
components/solid/firmware/hdl/sc_channels.vhd
View file @ 0e13ce4b
......@@ -31,7 +31,7 @@ entity sc_channels is
d_n: in std_logic_vector(N_CHAN - 1 downto 0);
sync_ctrl: in std_logic_vector(3 downto 0);
sctr: in std_logic_vector(13 downto 0);
rand: in std_logic_vector(13 downto 0);
fake: in std_logic_vector(13 downto 0);
nzs_en: in std_logic;
zs_en: in std_logic;
keep: in std_logic_vector(N_CHAN - 1 downto 0);
......@@ -111,7 +111,7 @@ begin
q_test => q_test(i),
sync_ctrl => sync_ctrl,
sctr => sctr,
rand => rand,
fake => fake,
nzs_en => nzs_en,
zs_en => zs_en,
keep => keep(i),
......
components/solid/firmware/hdl/sc_daq.vhd
View file @ 0e13ce4b
......@@ -50,6 +50,7 @@ architecture rtl of sc_daq is
signal sctr: std_logic_vector(47 downto 0);
signal trig_en, nzs_en, zs_en, chan_err: std_logic;
signal trig_keep, trig_flush, trig_veto: std_logic_vector(N_CHAN - 1 downto 0);
signal fake: std_logic_vector(13 downto 0);
signal chan_trig: sc_trig_array;
signal link_d, link_q: std_logic_vector(15 downto 0);
signal link_d_valid, link_q_valid, link_ack: std_logic;
......@@ -88,7 +89,19 @@ begin
);
clk40 <= clk40_i;
-- Fake data generator
faker: entity work.sc_fake
port map(
clk => ipb_clk,
rst => ipb_rst,
ipb_in => ipb_in_fake,
ipb_out => ipb_out_fake,
rand => rand,
fake => fake
);
-- Data channels
chans: entity work.sc_channels
......@@ -106,7 +119,7 @@ begin
d_n => d_n,
sync_ctrl => sync_ctrl,
sctr => sctr(13 downto 0),
rand => rand(13 downto 0),
fake => fake,
nzs_en => nzs_en,
zs_en => zs_en,
keep => trig_keep,
......
components/solid/firmware/hdl/sc_fake.vhd 0 → 100644
View file @ 0e13ce4b
-- sc_fake
--
-- Fake data generator for trigger testing
--
-- Dave Newbold, June 2017
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
use work.ipbus.all;
use work.ipbus_reg_types.all;
entity sc_fake is
port(
clk: in std_logic; -- ipbus clock (nominally ~30MHz) & reset
rst: in std_logic;
ipb_in: in ipb_wbus;
ipb_out: out ipb_rbus;
rand: in std_logic_vector(31 downto 0);
fake: out std_logic_vector(13 downto 0)
);
end sc_fake
architecture rtl of sc_fake is
begin
ipb_out <= IPB_RBUS_NULL;
fake <= rand(13 downto 0);
end rtl;
projects/64ch/addr_table/top.xml
View file @ 0e13ce4b
......@@ -3,8 +3,8 @@
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="io" address="0x20" module="file://sc_io_64chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="tlink" address="0x50" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x60" module="file://sc_trig.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
<!-- <node id="mon" address="0x90" module="file://sc_temp.xml"/> -->
</node>
projects/64ch/addr_table/top_sim.xml
View file @ 0e13ce4b
......@@ -2,7 +2,8 @@
<node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x8" module="file://sc_chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="tlink" address="0x50" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x60" module="file://sc_trig.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
</node>
projects/8ch/addr_table/top.xml
View file @ 0e13ce4b
......@@ -3,8 +3,9 @@
<node id="chan" address="0x10" module="file://sc_chan.xml"/>
<node id="io" address="0x20" module="file://sc_io.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="tlink" address="0x50" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x60" module="file://sc_trig.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
<!-- <node id="mon" address="0x90" module="file://sc_temp.xml"/> -->
</node>
projects/8ch/addr_table/top_sim.xml
View file @ 0e13ce4b
......@@ -2,7 +2,8 @@
<node id="csr" address="0x0" module="file://payload.xml"/>
<node id="chan" address="0x8" module="file://sc_chan.xml"/>
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="tlink" address="0x50" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x60" module="file://sc_trig.xml"/>
<node id="fake" address="0x50" fwinfo="endpoint;width=0"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
</node>
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