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euro-adc-65m-14b-40cha-gw
Commit 447dfa74 authored by Dave Newbold's avatar Dave Newbold
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Adding channel trigger masks

parent 2bfb87c9
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Showing with 37 additions and 17 deletions
components/solid/addr_table/sc_chan.xml
View file @ 447dfa74
......@@ -3,8 +3,7 @@
<node id="ctrl" address="0x0">
<node id="en_sync" mask="0x1"/>
<node id="en_buf" mask="0x2"/>
<node id="en_trig" mask="0x4"/>
<node id="invert" mask="0x8"/>
<node id="invert" mask="0x4"/>
<node id="mode" mask="0x30"/>
<node id="src" mask="0xc0"/>
<node id="zs_thresh" mask="0x3fff0000"/>
......
components/solid/addr_table/sc_trig.xml
View file @ 447dfa74
......@@ -20,4 +20,5 @@
<node id="data" address="0x1" mode="port"/>
</node>
<node id="seq" address="0x8" module="file://sc_seq.xml"/>
<node id="masks" address="0x10" mode="block" size="0x10" description="channel trigger masks" fwinfo="endpoint;width=4">
</node>
components/solid/firmware/hdl/sc_chan.vhd
View file @ 447dfa74
......@@ -67,12 +67,12 @@ architecture rtl of sc_chan is
signal d_in, d_in_i, d_buf: std_logic_vector(13 downto 0);
signal d_c: std_logic_vector(1 downto 0);
signal slip, chan_rst, buf_we, inc: std_logic;
signal ctrl_en_sync, ctrl_en_buf, ctrl_en_trig, ctrl_invert: std_logic;
signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic;
signal ctrl_mode, ctrl_src: std_logic_vector(1 downto 0);
signal cap_full, buf_full, dr_full, dr_warn: std_logic;
signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen, trig_en: std_logic;
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen: std_logic;
begin
......@@ -109,8 +109,7 @@ begin
ctrl_en_sync <= ctrl(0)(0);
ctrl_en_buf <= ctrl(0)(1);
ctrl_en_trig <= ctrl(0)(2);
ctrl_invert <= ctrl(0)(3);
ctrl_invert <= ctrl(0)(2);
ctrl_mode <= ctrl(0)(5 downto 4);
ctrl_src <= ctrl(0)(7 downto 6);
......@@ -213,8 +212,6 @@ begin
-- Local triggers
trig_en <= nzs_en and ctrl_en_trig;
ctrig: entity work.sc_chan_trig
generic map(
VAL_WIDTH => 14
......
components/solid/firmware/hdl/sc_trig.vhd
View file @ 447dfa74
......@@ -52,6 +52,8 @@ architecture rtl of sc_trig is
signal ctrl: ipb_reg_v(0 downto 0);
signal stat: ipb_reg_v(1 downto 0);
signal ctrl_dtmon_en: std_logic;
signal masks: ipb_reg_v(N_CHAN_TRG * 2 - 1 downto 0);
signal ctrig: sc_trig_array;
signal lq: std_logic_vector(15 downto 0);
signal rveto, lvalid, lack, mark, err: std_logic;
signal veto_p, veto_i, keep_i, flush_i: std_logic_vector(N_CHAN - 1 downto 0);
......@@ -113,6 +115,27 @@ begin
end if;
end if;
end process;
-- Channel trigger masks
masks: entity work.ipbus_reg_v
generic map(
N_REG => N_CHAN_TRG * 2
)
port map(
clk => clk,
reset => rst,
ipbus_in => ipbw(N_SLV_MASKS),
ipbus_out => ipbr(N_SLV_MASKS),
q => masks
);
mgen: for i in N_CHAN_TRG - 1 downto 0 generate
signal m: std_logic_vector(63 downto 0);
begin
m <= masks(i * 2 + 1) & masks(i * 2);
ctrig(i) <= trig(i) and m(N_CHAN - 1 downto 0);
end generate;
-- Local trigger logic
......@@ -128,7 +151,7 @@ begin
mark => mark,
sctr => sctr,
rand => rand,
chan_trig => trig,
chan_trig => ctrig,
trig_q => lq,
trig_valid => lvalid,
trig_ack => lack,
......
projects/64ch/addr_table/top.xml
View file @ 447dfa74
......@@ -5,6 +5,6 @@
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
</node>
projects/64ch/addr_table/top_sim.xml
View file @ 447dfa74
......@@ -4,6 +4,6 @@
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
</node>
projects/8ch/addr_table/top.xml
View file @ 447dfa74
......@@ -5,7 +5,7 @@
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
<!-- <node id="mon" address="0x90" module="file://sc_temp.xml"/> -->
</node>
projects/8ch/addr_table/top_sim.xml
View file @ 447dfa74
......@@ -4,6 +4,6 @@
<node id="timing" address="0x40" module="file://sc_timing.xml"/>
<node id="fake" address="0x50" module="file://sc_fake.xml"/>
<node id="tlink" address="0x60" fwinfo="endpoint;width=0"/>
<node id="trig" address="0x70" module="file://sc_trig.xml"/>
<node id="roc" address="0x80" module="file://sc_roc.xml"/>
<node id="trig" address="0x80" module="file://sc_trig.xml"/>
<node id="roc" address="0xa0" module="file://sc_roc.xml"/>
</node>
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