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euro-adc-65m-14b-40cha-gw
Commit 2bfb87c9 authored by Dave Newbold's avatar Dave Newbold
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Fixing trigger logic

parent 43c783cc
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Showing with 8 additions and 4 deletions
components/solid/firmware/hdl/sc_trig_gen_or.vhd
View file @ 2bfb87c9
......@@ -35,10 +35,12 @@ architecture rtl of sc_trig_gen_or is
signal mark_d, mark_dd: std_logic;
signal mark_del: std_logic_vector(DELAY - 1 downto 0);
signal v: std_logic;
begin
mark_del <= mark_del(DELAY - 2 downto 0) & mark when rising_edge(clk);
valid <= (valid or (or_reduce(chan_trig(TBIT)) and mark_del(DELAY - 1))) and not (ack or not en) when rising_edge(clk);
v <= (v or (or_reduce(chan_trig(TBIT)) and mark_del(DELAY - 1))) and not (ack or not en) when rising_edge(clk);
valid <= v;
end rtl;
components/solid/firmware/hdl/sc_trig_gen_random.vhd
View file @ 2bfb87c9
......@@ -36,6 +36,7 @@ architecture rtl of sc_trig_gen_random is
signal mask: std_logic_vector(23 downto 0);
signal rtrig, force_c, force_d: std_logic;
signal v: std_logic;
begin
......@@ -54,6 +55,7 @@ begin
rtrig <= ((not mode(0) and not or_reduce(rand(mask'range) and mask)) or
(mode(0) and not or_reduce(sctr(BLK_RADIX + mask'left downto BLK_RADIX) and mask))) and mode(1);
valid <= (valid or ((rtrig or force_c) and mark)) and not (ack or not en) when rising_edge(clk);
v <= (v or ((rtrig or force_c) and mark)) and not (ack or not en) when rising_edge(clk);
valid <= v;
end rtl;
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