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euro-adc-65m-14b-40cha-gw
Commit 43c783cc authored by Dave Newbold's avatar Dave Newbold
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Fixing trigger logic

parent cf29b41a
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Showing with 5 additions and 5 deletions
components/solid/firmware/hdl/sc_local_trig.vhd
View file @ 43c783cc
......@@ -52,7 +52,7 @@ architecture rtl of sc_local_trig is
signal ctrl_trig_force: std_logic;
signal ctrl_rnd_div: std_logic_vector(5 downto 0);
signal tv, te, ta, tc: std_logic_vector(N_TRG - 1 downto 0);
signal s: integer range N_TRG downto 0;
signal s: integer range N_TRG - 1 downto 0;
signal ch: integer range 2 ** ro_ctr'length - 1 downto 0;
signal ch_i: integer range N_CHAN - 1 downto 0 := 0;
signal go, blkend, rveto_d, last_gasp, hoorah: std_logic;
......@@ -155,8 +155,8 @@ begin
process(te)
begin
for i in te'range loop
s <= 0;
s <= 0;
for i in te'reverse_range loop
if te(i) = '1' then
s <= i;
end if;
......
components/solid/firmware/hdl/sc_trig_gen_or.vhd
View file @ 43c783cc
......@@ -39,6 +39,6 @@ architecture rtl of sc_trig_gen_or is
begin
mark_del <= mark_del(DELAY - 2 downto 0) & mark when rising_edge(clk);
valid <= (or_reduce(chan_trig(TBIT)) and mark_del(DELAY - 1)) and not (ack or not en) when rising_edge(clk);
valid <= (valid or (or_reduce(chan_trig(TBIT)) and mark_del(DELAY - 1))) and not (ack or not en) when rising_edge(clk);
end rtl;
components/solid/firmware/hdl/sc_trig_gen_random.vhd
View file @ 43c783cc
......@@ -54,6 +54,6 @@ begin
rtrig <= ((not mode(0) and not or_reduce(rand(mask'range) and mask)) or
(mode(0) and not or_reduce(sctr(BLK_RADIX + mask'left downto BLK_RADIX) and mask))) and mode(1);
valid <= ((rtrig or force_c) and mark) and not (ack or not en) when rising_edge(clk);
valid <= (valid or ((rtrig or force_c) and mark)) and not (ack or not en) when rising_edge(clk);
end rtl;
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