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euro-adc-65m-14b-40cha-gw
Commit cf29b41a authored by Dave Newbold's avatar Dave Newbold
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Adding trigger enable bit to channel

parent c7a8bc03
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Showing with 14 additions and 9 deletions
components/solid/addr_table/sc_chan.xml
View file @ cf29b41a
......@@ -3,7 +3,8 @@
<node id="ctrl" address="0x0">
<node id="en_sync" mask="0x1"/>
<node id="en_buf" mask="0x2"/>
<node id="invert" mask="0x4"/>
<node id="en_trig" mask="0x4"/>
<node id="invert" mask="0x8"/>
<node id="mode" mask="0x30"/>
<node id="src" mask="0xc0"/>
<node id="zs_thresh" mask="0x3fff0000"/>
......
components/solid/firmware/hdl/sc_chan.vhd
View file @ cf29b41a
......@@ -67,12 +67,12 @@ architecture rtl of sc_chan is
signal d_in, d_in_i, d_buf: std_logic_vector(13 downto 0);
signal d_c: std_logic_vector(1 downto 0);
signal slip, chan_rst, buf_we, inc: std_logic;
signal ctrl_en_sync, ctrl_en_buf, ctrl_invert: std_logic;
signal ctrl_en_sync, ctrl_en_buf, ctrl_en_trig, ctrl_invert: std_logic;
signal ctrl_mode, ctrl_src: std_logic_vector(1 downto 0);
signal cap_full, buf_full, dr_full, dr_warn: std_logic;
signal sctr_p: std_logic_vector(11 downto 0);
signal dr_d: std_logic_vector(31 downto 0);
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen: std_logic;
signal ro_en, keep_i, flush_i, err_i, req, blkend, dr_blkend, dr_wen, trig_en: std_logic;
begin
......@@ -109,7 +109,8 @@ begin
ctrl_en_sync <= ctrl(0)(0);
ctrl_en_buf <= ctrl(0)(1);
ctrl_invert <= ctrl(0)(2);
ctrl_en_trig <= ctrl(0)(2);
ctrl_invert <= ctrl(0)(3);
ctrl_mode <= ctrl(0)(5 downto 4);
ctrl_src <= ctrl(0)(7 downto 6);
......@@ -212,6 +213,8 @@ begin
-- Local triggers
trig_en <= nzs_en and ctrl_en_trig;
ctrig: entity work.sc_chan_trig
generic map(
VAL_WIDTH => 14
......
components/solid/firmware/hdl/sc_chan_trig.vhd
View file @ cf29b41a
......@@ -37,6 +37,7 @@ architecture rtl of sc_chan_trig is
signal ctrl: ipb_reg_v(2 downto 0);
signal dd: std_logic_vector(13 downto 0);
signal trig_i: std_logic_vector(N_CHAN_TRG - 1 downto 0);
begin
......@@ -66,7 +67,7 @@ begin
clr => mark,
d => dd,
threshold => ctrl(0)(VAL_WIDTH - 1 downto 0),
trig => trig(0)
trig => trig_i(0)
);
trg1: entity work.sc_ctrig_npeaks -- peaks-above-threshold trigger, delay = 2
......@@ -82,7 +83,7 @@ begin
cthresh => ctrl(1)(24 downto 16),
wsize => ctrl(1)(31 downto 28),
pthresh => ctrl(1)(VAL_WIDTH - 1 downto 0),
trig => trig(1)
trig => trig_i(1)
);
trg2: entity work.sc_ctrig_tot -- time-over-threshold trigger, delay = 1
......@@ -98,7 +99,9 @@ begin
cthresh => ctrl(2)(24 downto 16),
wsize => ctrl(2)(31 downto 28),
pthresh => ctrl(2)(VAL_WIDTH - 1 downto 0),
trig => trig(2)
trig => trig_i(2)
);
trig <= trig_i when en = '1' else (others => '0');
end rtl;
components/solid/firmware/hdl/sc_ctrig_window.vhd
View file @ cf29b41a
......@@ -28,8 +28,6 @@ entity sc_ctrig_window is
end sc_ctrig_window;
architecture rtl of sc_ctrig_window is
constant WINDOW_LEN: integer := BLK_RADIX;
signal w, f: std_logic_vector(2 ** wsize'length downto 0);
signal r: std_logic;
......
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