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euro-adc-65m-14b-40cha-gw
Commit 1b64d745 authored by Dave Newbold's avatar Dave Newbold
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Merge branch 'master' of https://bitbucket.org/solidexperiment/solid_firmware

parents 09add8ca 953f5237
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Showing with 9 additions and 8 deletions
components/solid/firmware/hdl/ipbus_decode_sc_trig.vhd
View file @ 1b64d745
...@@ -17,13 +17,13 @@ package ipbus_decode_sc_trig is ...@@ -17,13 +17,13 @@ package ipbus_decode_sc_trig is
subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0); subtype ipbus_sel_t is std_logic_vector(IPBUS_SEL_WIDTH - 1 downto 0);
function ipbus_sel_sc_trig(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t; function ipbus_sel_sc_trig(addr : in std_logic_vector(31 downto 0)) return ipbus_sel_t;
-- START automatically generated VHDL the Fri Jul 14 14:14:53 2017 -- START automatically generated VHDL the Wed Aug 23 15:54:14 2017
constant N_SLV_CSR: integer := 0; constant N_SLV_CSR: integer := 0;
constant N_SLV_LOC_MASK: integer := 1; constant N_SLV_LOC_MASK: integer := 1;
constant N_SLV_ZS_CFG: integer := 2; constant N_SLV_ZS_CFG: integer := 2;
constant N_SLV_DTMON: integer := 3; constant N_SLV_DTMON: integer := 3;
constant N_SLV_SEQ: integer := 4; constant N_SLV_SEQ: integer := 4;
constant N_SLV_CHAN_MASK: integer := 5; constant N_SLV_MASKS: integer := 5;
constant N_SLAVES: integer := 6; constant N_SLAVES: integer := 6;
-- END automatically generated VHDL -- END automatically generated VHDL
...@@ -36,7 +36,7 @@ package body ipbus_decode_sc_trig is ...@@ -36,7 +36,7 @@ package body ipbus_decode_sc_trig is
variable sel: ipbus_sel_t; variable sel: ipbus_sel_t;
begin begin
-- START automatically generated VHDL the Fri Jul 14 14:14:53 2017 -- START automatically generated VHDL the Wed Aug 23 15:54:14 2017
if std_match(addr, "---------------------------000--") then if std_match(addr, "---------------------------000--") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000001c sel := ipbus_sel_t(to_unsigned(N_SLV_CSR, IPBUS_SEL_WIDTH)); -- csr / base 0x00000000 / mask 0x0000001c
elsif std_match(addr, "---------------------------00100") then elsif std_match(addr, "---------------------------00100") then
...@@ -48,7 +48,7 @@ package body ipbus_decode_sc_trig is ...@@ -48,7 +48,7 @@ package body ipbus_decode_sc_trig is
elsif std_match(addr, "---------------------------01---") then elsif std_match(addr, "---------------------------01---") then
sel := ipbus_sel_t(to_unsigned(N_SLV_SEQ, IPBUS_SEL_WIDTH)); -- seq / base 0x00000008 / mask 0x00000018 sel := ipbus_sel_t(to_unsigned(N_SLV_SEQ, IPBUS_SEL_WIDTH)); -- seq / base 0x00000008 / mask 0x00000018
elsif std_match(addr, "---------------------------1----") then elsif std_match(addr, "---------------------------1----") then
sel := ipbus_sel_t(to_unsigned(N_SLV_CHAN_MASK, IPBUS_SEL_WIDTH)); -- chan_mask / base 0x00000010 / mask 0x00000010 sel := ipbus_sel_t(to_unsigned(N_SLV_MASKS, IPBUS_SEL_WIDTH)); -- masks / base 0x00000010 / mask 0x00000010
-- END automatically generated VHDL -- END automatically generated VHDL
else else
......
components/solid/firmware/hdl/sc_rtrig.vhd
View file @ 1b64d745
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all; use ieee.std_logic_misc.all;
use work.ipbus.all; use work.ipbus.all;
...@@ -38,9 +39,9 @@ architecture rtl of sc_rtrig is ...@@ -38,9 +39,9 @@ architecture rtl of sc_rtrig is
begin begin
mask: entity work.ipbus_reg_v reg: entity work.ipbus_reg_v
generic map( generic map(
N_REG => N_CHAN_TRG * 2 N_REG => 1
) )
port map( port map(
clk => clk, clk => clk,
......
components/solid/firmware/hdl/sc_trig.vhd
View file @ 1b64d745
...@@ -136,8 +136,8 @@ begin ...@@ -136,8 +136,8 @@ begin
port map( port map(
clk => clk, clk => clk,
reset => rst, reset => rst,
ipbus_in => ipbw(N_SLV_CHAN_MASK), ipbus_in => ipbw(N_SLV_MASKS),
ipbus_out => ipbr(N_SLV_CHAN_MASK), ipbus_out => ipbr(N_SLV_MASKS),
q => masks q => masks
); );
......
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