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euro-adc-65m-14b-40cha-gw
Commit 15fcf147 authored by Dave Newbold's avatar Dave Newbold
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Testing bug fix in timing startup

parent fdf98a27
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Showing with 15 additions and 8 deletions
components/solid/firmware/hdl/sc_timing_startup.vhd
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...@@ -44,14 +44,21 @@ begin ...@@ -44,14 +44,21 @@ begin
up <= '1'; up <= '1';
end if; end if;
if up = '1' then if up = '1' then
if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then -- if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 then -- if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 then
nzs_en <= '1'; -- nzs_en <= '1';
elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 + NZS_BLKS then -- elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 + NZS_BLKS then
zs_en <= '1'; -- zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = 7 + NZS_BLKS + ZS_BLKS then -- elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = 7 + NZS_BLKS + ZS_BLKS then
trig_en <= '1'; -- trig_en <= '1';
end if; -- end if;
-- end if;
if unsigned(sctr(7 + BLK_RADIX downto 0)) = 9 * 2 ** BLK_RADIX - 1 then
nzs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto 0)) = (9 + NZS_BLKS) * 2 ** BLK_RADIX + ZS_DEL then
zs_en <= '1';
elsif unsigned(sctr(7 + BLK_RADIX downto 0)) = (10 + NZS_BLKS + ZS_BLKS) * 2 ** BLK_RADIX then
trig_en <= '1'
end if; end if;
end if; end if;
end if; end if;
......
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