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euro-adc-65m-14b-40cha
euro-adc-65m-14b-40cha-gw
Commits
15fcf147
Commit
15fcf147
authored
Nov 17, 2017
by
Dave Newbold
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Testing bug fix in timing startup
parent
fdf98a27
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15 additions
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8 deletions
+15
-8
sc_timing_startup.vhd
components/solid/firmware/hdl/sc_timing_startup.vhd
+15
-8
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components/solid/firmware/hdl/sc_timing_startup.vhd
View file @
15fcf147
...
...
@@ -44,14 +44,21 @@ begin
up
<=
'1'
;
end
if
;
if
up
=
'1'
then
if
and_reduce
(
std_logic_vector
(
sctr
(
BLK_RADIX
-
1
downto
0
)))
=
'1'
then
if
unsigned
(
sctr
(
3
+
BLK_RADIX
downto
BLK_RADIX
))
=
8
then
nzs_en
<=
'1'
;
elsif
unsigned
(
sctr
(
3
+
BLK_RADIX
downto
BLK_RADIX
))
=
8
+
NZS_BLKS
then
zs_en
<=
'1'
;
elsif
unsigned
(
sctr
(
7
+
BLK_RADIX
downto
BLK_RADIX
))
=
7
+
NZS_BLKS
+
ZS_BLKS
then
trig_en
<=
'1'
;
end
if
;
-- if and_reduce(std_logic_vector(sctr(BLK_RADIX - 1 downto 0))) = '1' then
-- if unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 then
-- nzs_en <= '1';
-- elsif unsigned(sctr(3 + BLK_RADIX downto BLK_RADIX)) = 8 + NZS_BLKS then
-- zs_en <= '1';
-- elsif unsigned(sctr(7 + BLK_RADIX downto BLK_RADIX)) = 7 + NZS_BLKS + ZS_BLKS then
-- trig_en <= '1';
-- end if;
-- end if;
if
unsigned
(
sctr
(
7
+
BLK_RADIX
downto
0
))
=
9
*
2
**
BLK_RADIX
-
1
then
nzs_en
<=
'1'
;
elsif
unsigned
(
sctr
(
7
+
BLK_RADIX
downto
0
))
=
(
9
+
NZS_BLKS
)
*
2
**
BLK_RADIX
+
ZS_DEL
then
zs_en
<=
'1'
;
elsif
unsigned
(
sctr
(
7
+
BLK_RADIX
downto
0
))
=
(
10
+
NZS_BLKS
+
ZS_BLKS
)
*
2
**
BLK_RADIX
then
trig_en
<=
'1'
end
if
;
end
if
;
end
if
;
...
...
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