This was include in commits from lnls-bpm/bpm-gw@09f35bd8f7 to
lnls-bpm/bpm-gw@3c537b769f

The FPGA gateware was changed to uniformize
the WB register map for the FMC ACTIVE part.

Now, if EPICS IOCs are started with systemd
they have a dependency with bpm-sw@.service

Removing the socket handler on *_cfg handle was wrong
as the devio_destroy_smio () already calls
devio_destroy_actor (), which, in turn, removes
the socket from the reader.

Also, as we expect only a single message on the
handler, it`s safer and cleaner to not poll the socket
until there is no message.

If an SMIO fails for some reason, continue to spawn
the other ones.

This was changed on commit 5a769af3

As an optimization, we registered the SMIO message
and SMIO config handlers before creating the actor.

For the first case this is OK, as as register the
handler to an existing socket creted by
zsys_create_pipe ().

For the second case the registered socket does not
yet exist, as it will be creted by zactor_new ().

This fixes #114 github issue

It's easier to standardize the initial EPICS
BPM ID from 1 to 24 instead of from 0 to 23.

In this way, the reported ID to clients stau consistent
with the FPGA driver, as well.

In this way, we avoid creating an SMIO instance
without a listener on the other side.

This allows us to clean all of the generated
APPS objects

This would help solving a long-standing issue
of not having the DEVIO looping through messages
before spawing all of the SMIO modules, which used
to happen before the main loop

We are now using a reactor API, zloop, which is better
coded and more standard than a custom poller loop.

We are now using a reactor API, zloop, which is better
coded and more standard than a custom poller loop.

Instead of using the index of the smio_mod_dispatch table,
which is weak and error prone, we use a handler pointer instead.

The system integration will take care of
daemonizing the whole set of process if needed

The specified address is a one-hot encoded.
So, for each ADC, only 1 bit must be set
in the order required by that specific ADC.

The MSB of the ISLA216P transaction must be
R/W bit followed by Length specification,
Register address and data (for write transactions)

On BIDIR mode, the received data is on base address
register RX0 and not RX0_SINGLE

If we are using SPI in bidir mode, the character
length should be copied to the 7 LSB of
"SPI_PROTO_REG_CFG_BIDIR" and not
"SPI_PROTO_REG_CTRL"

It should be comparing with the number of bytes,
not with SUCCESS conditions.