- Jul 18, 2016
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Lucas Russo authored
Now, instead of spawning a DEVIO BE application and that application, in turn, spawn the DEVIO FE, we are using a more modular approach in that each DEVIO BE or DEVIO FE spawns a single application. We will rely on the system integration (such as systemd) to take care of our dependencies for us.
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- May 20, 2016
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Lucas Russo authored
Github commit lnls-dig/bpm-gw@d952234374 changed it. So we update it here.
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- May 17, 2016
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Lucas Russo authored
Added "_BASE" to name address, for consistency with existing names.
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Lucas Russo authored
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- May 16, 2016
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Lucas Russo authored
This is very useful on setting/getting registers in modules that have multiple channels with the same register definitions.
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Lucas Russo authored
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- May 09, 2016
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Lucas Russo authored
This way avoids users needing to know how this is implemented internally and, obviously, decreases the chances of error.
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Lucas Russo authored
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- Apr 26, 2016
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Lucas Russo authored
In this way, we can standardize how the functions are called and handled.
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Lucas Russo authored
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- Apr 24, 2016
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Lucas Russo authored
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Lucas Russo authored
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- Apr 20, 2016
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Lucas Russo authored
This is necessary as lnls-dig/bpm-gw@6a78088ab1 and lnls-dig/bpm-gw@950b4b2d18
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- Apr 19, 2016
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Lucas Russo authored
In this way we can guarantee that these functions will be thread-safe even if other SMIOs calls them.
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Lucas Russo authored
The previous implementation was not thread-safe.
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Lucas Russo authored
We should replace this functions by sending a message to the DEVIO instance through the PIPE management.
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This opens new possibilities for chaining SMIOs. For instance, the FMC_250M SMIO can register 2 more SMIOs: FMC_ADC_COMMON and FMC_ACTIVE_CLK
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This was include in commits from lnls-bpm/bpm-gw@09f35bd8f7 to lnls-bpm/bpm-gw@3c537b769f
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Lucas Russo authored
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- Apr 18, 2016
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Lucas Russo authored
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- Apr 15, 2016
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Lucas Russo authored
The FPGA gateware was changed to uniformize the WB register map for the FMC ACTIVE part.
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- Mar 31, 2016
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Lucas Russo authored
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Lucas Russo authored
We are now using a reactor API, zloop, which is better coded and more standard than a custom poller loop.
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Lucas Russo authored
Instead of using the index of the smio_mod_dispatch table, which is weak and error prone, we use a handler pointer instead.
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- Mar 24, 2016
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Lucas Russo authored
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Lucas Russo authored
The MSB of the ISLA216P transaction must be R/W bit followed by Length specification, Register address and data (for write transactions)
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- Mar 23, 2016
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Lucas Russo authored
If we are using SPI in bidir mode, the character length should be copied to the 7 LSB of "SPI_PROTO_REG_CFG_BIDIR" and not "SPI_PROTO_REG_CTRL"
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
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Lucas Russo authored
This is the correct place for them as this files could be used for other modules.
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Lucas Russo authored
This is the correct place for them as this files could be used for other modules.
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- Mar 22, 2016
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Lucas Russo authored
With this, we can specify if we want to use a bidirectional (three-mode) SPI or the regular one. This, of course, relies on hardware support.
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- Mar 02, 2016
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Lucas Russo authored
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