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David Cussans authored
( trigger output two clock cycles of 40MHz, trigger number on reset line being clocked out at 160MHz) * Added reset circuitry to DUTInterface_AIDA_rtl.vhd * Added one extra register of clk4x ( 160MHz ) to aid with timing closure ( although Vivado not reporting negative slack - so have probably got timing contraints wrong :-o )
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