DMTD offset clock close to the end of DAC range
Our DMTD offset clock was configured to be (1+1/16384)*f_ref with turned out to be close to the end of the DAC range. This combined with the fact that the actual DAC range was reduced by the problem in the SPEC design caused locking problems on a few boards running in higher temperatures.
The solution to this problem would be to modify the DMTD offset frequency so that we're close to the center of DAC range (i.e. we have more room in both directions to keep VCXO locked when temperature changes).