Skip to content

W
wr-switch-sw
Commit 8f856722 authored by Alessandro Rubini's avatar Alessandro Rubini
Browse files
Options

userspace/include: remove trailing blanks

parent b452cfbf
Hide whitespace changes
Inline Side-by-side
Showing with 22 additions and 22 deletions
userspace/include/hw/dmpll.h
View file @ 8f856722
...@@ -24,6 +24,6 @@ typedef struct { ...@@ -24,6 +24,6 @@ typedef struct {
int channel; int channel;
double phase_setpoint[4]; double phase_setpoint[4];
} dmpll_params_t; } dmpll_params_t;
#endif #endif
userspace/include/hw/endpoint_regs.h
View file @ 8f856722
...@@ -255,8 +255,8 @@ ...@@ -255,8 +255,8 @@
#define EP_AFR2_ETYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16) #define EP_AFR2_ETYPE_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define EP_AFR2_ETYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16) #define EP_AFR2_ETYPE_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for RAM: Event counters memory */ /* definitions for RAM: Event counters memory */
#define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */ #define EP_RMON_RAM_BYTES 0x00000080 /* size in bytes */
#define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */ #define EP_RMON_RAM_WORDS 0x00000020 /* size in 32-bit words, 32-bit aligned */
/* [0x0]: REG Endpoint Control Register */ /* [0x0]: REG Endpoint Control Register */
#define EP_REG_ECR 0x00000000 #define EP_REG_ECR 0x00000000
/* [0x4]: REG Timestamping Control Register */ /* [0x4]: REG Timestamping Control Register */
......
userspace/include/hw/fpga_regs.h
View file @ 8f856722
...@@ -30,9 +30,9 @@ extern volatile uint8_t *_fpga_base_virt; ...@@ -30,9 +30,9 @@ extern volatile uint8_t *_fpga_base_virt;
#define FPGA_BASE_EP_DP6 _FPGA_BUS_2_ADDR(12) #define FPGA_BASE_EP_DP6 _FPGA_BUS_2_ADDR(12)
#define FPGA_BASE_EP_DP7 _FPGA_BUS_2_ADDR(13) #define FPGA_BASE_EP_DP7 _FPGA_BUS_2_ADDR(13)
#define FPGA_BASE_PPS_GEN _FPGA_BUS_2_ADDR(14) #define FPGA_BASE_PPS_GEN _FPGA_BUS_2_ADDR(14)
#define FPGA_BASE_CALIBRATOR _FPGA_BUS_2_ADDR(15) #define FPGA_BASE_CALIBRATOR _FPGA_BUS_2_ADDR(15)
#define FPGA_BASE_RTU _FPGA_BUS_2_ADDR(16) #define FPGA_BASE_RTU _FPGA_BUS_2_ADDR(16)
#define FPGA_BASE_RTU_TESTUNIT _FPGA_BUS_2_ADDR(17) #define FPGA_BASE_RTU_TESTUNIT _FPGA_BUS_2_ADDR(17)
#define GPIO_REG_CODR 0x0 #define GPIO_REG_CODR 0x0
#define GPIO_REG_SODR 0x4 #define GPIO_REG_SODR 0x4
......
userspace/include/hw/hpll.h
View file @ 8f856722
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
#define HPLL_PD_GATE_32K 6 #define HPLL_PD_GATE_32K 6
#define HPLL_PD_GATE_64K 7 #define HPLL_PD_GATE_64K 7
// Frequency detector gating: // Frequency detector gating:
#define HPLL_FD_GATE_16K 0 #define HPLL_FD_GATE_16K 0
#define HPLL_FD_GATE_32K 1 #define HPLL_FD_GATE_32K 1
#define HPLL_FD_GATE_64K 2 #define HPLL_FD_GATE_64K 2
...@@ -27,8 +27,8 @@ ...@@ -27,8 +27,8 @@
#define HPLL_FD_GATE_2M 7 #define HPLL_FD_GATE_2M 7
#define HPLL_REFSEL_UP0_RBCLK 2 #define HPLL_REFSEL_UP0_RBCLK 2
#define HPLL_REFSEL_UP1_RBCLK 1 #define HPLL_REFSEL_UP1_RBCLK 1
#define HPLL_REFSEL_LOCAL 0 #define HPLL_REFSEL_LOCAL 0
typedef struct { typedef struct {
...@@ -37,12 +37,12 @@ typedef struct { ...@@ -37,12 +37,12 @@ typedef struct {
int phase_gain_steps; // number of phase gain (start to end) transition steps int phase_gain_steps; // number of phase gain (start to end) transition steps
uint64_t phase_gain_step_delay; // step delay for phase gain adjustment (in microseconds) uint64_t phase_gain_step_delay; // step delay for phase gain adjustment (in microseconds)
int N, delta; // divider settings: output_freq = input_freq * (N / (N+delta)) int N, delta; // divider settings: output_freq = input_freq * (N / (N+delta))
int freq_gating; // frequency detector gating int freq_gating; // frequency detector gating
int phase_gating; // phase detector gating int phase_gating; // phase detector gating
int ref_sel; // reference clock select int ref_sel; // reference clock select
int force_freqmode; // force frequency lock mode int force_freqmode; // force frequency lock mode
......
userspace/include/hw/pio_pins.h
View file @ 8f856722
...@@ -22,10 +22,10 @@ extern const pio_pin_t PIN_fled6[]; ...@@ -22,10 +22,10 @@ extern const pio_pin_t PIN_fled6[];
extern const pio_pin_t PIN_fled7[]; extern const pio_pin_t PIN_fled7[];
// uTCA front panel LEDs // uTCA front panel LEDs
extern const pio_pin_t PIN_uled0[]; extern const pio_pin_t PIN_uled0[];
extern const pio_pin_t PIN_uled1[]; extern const pio_pin_t PIN_uled1[];
extern const pio_pin_t PIN_uled2[]; extern const pio_pin_t PIN_uled2[];
extern const pio_pin_t PIN_uled3[]; extern const pio_pin_t PIN_uled3[];
// AD9516 PLL control signals // AD9516 PLL control signals
extern const pio_pin_t PIN_ad9516_cs[]; extern const pio_pin_t PIN_ad9516_cs[];
......
userspace/include/hw/watchdog.h
View file @ 8f856722
...@@ -8,12 +8,12 @@ ...@@ -8,12 +8,12 @@
#define MBL_LED_LINK 0 #define MBL_LED_LINK 0
#define MBL_LED_ACT 1 #define MBL_LED_ACT 1
#define MBL_LED_OFF 0 #define MBL_LED_OFF 0
#define MBL_LED_ON 1 #define MBL_LED_ON 1
#define MBL_LED_BLINK_SLOW 2 #define MBL_LED_BLINK_SLOW 2
#define MBL_LED_BLINK_FAST 3 #define MBL_LED_BLINK_FAST 3
#define MBL_FEEDBACK_TX 1 #define MBL_FEEDBACK_TX 1
#define MBL_FEEDBACK_RX 2 #define MBL_FEEDBACK_RX 2
#define MBL_FEEDBACK_OFF 3 #define MBL_FEEDBACK_OFF 3
......
userspace/include/hw/wrsw_rtu_wb.h
View file @ 8f856722
...@@ -396,14 +396,14 @@ ...@@ -396,14 +396,14 @@
#define RTU_MFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6) #define RTU_MFIFO_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 6)
#define RTU_MFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6) #define RTU_MFIFO_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 6)
/* definitions for RAM: Hash collisions memory (HCAM) */ /* definitions for RAM: Hash collisions memory (HCAM) */
#define RTU_HCAM_BYTES 0x00000800 /* size in bytes */ #define RTU_HCAM_BYTES 0x00000800 /* size in bytes */
#define RTU_HCAM_WORDS 0x00000200 /* size in 32-bit words, 32-bit aligned */ #define RTU_HCAM_WORDS 0x00000200 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: Aging bitmap for main hashtable */ /* definitions for RAM: Aging bitmap for main hashtable */
#define RTU_ARAM_MAIN_BYTES 0x00000400 /* size in bytes */ #define RTU_ARAM_MAIN_BYTES 0x00000400 /* size in bytes */
#define RTU_ARAM_MAIN_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */ #define RTU_ARAM_MAIN_WORDS 0x00000100 /* size in 32-bit words, 32-bit aligned */
/* definitions for RAM: VLAN table (VLAN_TAB) */ /* definitions for RAM: VLAN table (VLAN_TAB) */
#define RTU_VLAN_TAB_BYTES 0x00004000 /* size in bytes */ #define RTU_VLAN_TAB_BYTES 0x00004000 /* size in bytes */
#define RTU_VLAN_TAB_WORDS 0x00001000 /* size in 32-bit words, 32-bit aligned */ #define RTU_VLAN_TAB_WORDS 0x00001000 /* size in 32-bit words, 32-bit aligned */
/* [0x0]: REG RTU Global Control Register */ /* [0x0]: REG RTU Global Control Register */
#define RTU_REG_GCR 0x00000000 #define RTU_REG_GCR 0x00000000
/* [0x4]: REG Aging register for HCAM */ /* [0x4]: REG Aging register for HCAM */
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment