wbgen-regs: new input wb files and output headers

This is the new input (*.wb) and output (*.h) files for device registers. I was making a huge mess with the copying and filtering, so I decided to make order. The previous commit adds the engine (Makefile), and the still previous removed stuff I committed by error. Now this part is stable I hope.

wbgen-regs: new input wb files and output headers
This is the new input (*.wb) and output (*.h) files for device registers. I was making a huge mess with the copying and filtering, so I decided to make order. The previous commit adds the engine (Makefile), and the still previous removed stuff I committed by error. Now this part is stable I hope.
56dec5ce · Alessandro Rubini · d8d928a7 · 56dec5ce · 56dec5ce · 56dec5ce
Commit 56dec5ce authored Nov 28, 2010 by Alessandro Rubini
10 changed files
--- a/wbgen-regs/calib-regs.h
+++ b/wbgen-regs/calib-regs.h
@@ -2,17 +2,16 @@
  Register definitions for slave core: DMTD PHY Calibrator

  * File           : calib-regs.h
-  * Author         : auto-generated by wbgen2 from wrsw_calibrator_dmtd.wb
-  * Created        : Tue Nov 23 13:47:20 2010
+  * Author         : auto-generated by wbgen2 from calib-regs.wb
  * Standard       : ANSI C

-    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_calibrator_dmtd.wb
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE calib-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

 */

-#ifndef __WBGEN2_REGDEFS_WRSW_CALIBRATOR_DMTD_WB
-#define __WBGEN2_REGDEFS_WRSW_CALIBRATOR_DMTD_WB
+#ifndef __WBGEN2_REGDEFS_CALIB
+#define __WBGEN2_REGDEFS_CALIB

 #include <linux/types.h>


--- a/wbgen-regs/calib-regs.wb
+++ b/wbgen-regs/calib-regs.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+	 name = "DMTD PHY Calibrator";
+	 prefix = "dpc";
+	 hdl_entity = "dmtd_calibrator_wb";
+
+	 reg {
+			name = "Control Register";
+			prefix = "CR";
+
+			field {
+				 name = "Enable";
+				 type = BIT;
+				 prefix = "EN";
+				 access_dev = READ_ONLY;
+				 access_bus = READ_WRITE;
+			};
+
+			field {
+				 name = "Compare clock select";
+				 prefix = "IN_SEL";
+				 type = SLV;
+				 size = 4;
+				 align = 8;
+				 access_dev = READ_ONLY;
+				 access_bus = READ_WRITE;
+			};
+
+			field {
+				 name = "DMTD averaging samples";
+				 prefix = "N_AVG";
+				 type = SLV;
+				 size = 12;
+				 align = 16;
+				 access_dev = READ_ONLY;
+				 access_bus = READ_WRITE;
+			};
+	 };
+
+	 reg {
+			name = "Status register";
+			prefix = "SR";
+
+			field {
+				 name = "Phase shift value";
+				 prefix = "PS_VAL";
+				 size = 24;
+				 type = SLV;
+				 access_dev = WRITE_ONLY;
+				 access_bus = READ_ONLY;
+			};
+
+			field {
+				 name = "Phase shift value ready";
+				 prefix = "PS_RDY";
+				 type = BIT;
+				 load = LOAD_EXT;
+				 access_dev = READ_WRITE;
+				 access_bus = READ_WRITE;
+			};
+	 };
+};
+
+
--- a/wbgen-regs/endpoint-regs.h
+++ b/wbgen-regs/endpoint-regs.h
@@ -2,17 +2,16 @@
  Register definitions for slave core: WR switch endpoint controller

  * File           : endpoint-regs.h
-  * Author         : auto-generated by wbgen2 from ep_wishbone_controller.wb
-  * Created        : Tue Nov 23 15:12:24 2010
+  * Author         : auto-generated by wbgen2 from endpoint-regs.wb
  * Standard       : ANSI C

-    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ep_wishbone_controller.wb
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE endpoint-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

 */

-#ifndef __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
-#define __WBGEN2_REGDEFS_EP_WISHBONE_CONTROLLER_WB
+#ifndef __WBGEN2_REGDEFS_ENDPOINT
+#define __WBGEN2_REGDEFS_ENDPOINT

 #include <linux/types.h>


--- a/wbgen-regs/endpoint-regs.wb
+++ b/wbgen-regs/endpoint-regs.wb
--- a/wbgen-regs/nic-regs.h
+++ b/wbgen-regs/nic-regs.h
@@ -2,17 +2,16 @@
  Register definitions for slave core: White Rabbit Switch NIC's spec

  * File           : nic-regs.h
-  * Author         : auto-generated by wbgen2 from wr_nic.wb
-  * Created        : Thu Nov 25 19:55:08 2010
+  * Author         : auto-generated by wbgen2 from nic-regs.wb
  * Standard       : ANSI C

-    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wr_nic.wb
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE nic-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

 */

-#ifndef __WBGEN2_REGDEFS_WR_NIC_WB
-#define __WBGEN2_REGDEFS_WR_NIC_WB
+#ifndef __WBGEN2_REGDEFS_NIC
+#define __WBGEN2_REGDEFS_NIC

 #include <linux/types.h>


--- a/wbgen-regs/nic-regs.wb
+++ b/wbgen-regs/nic-regs.wb
--- a/wbgen-regs/ppsg-regs.h
+++ b/wbgen-regs/ppsg-regs.h
@@ -2,17 +2,16 @@
  Register definitions for slave core: WR Switch PPS generator and RTC

  * File           : ppsg-regs.h
-  * Author         : auto-generated by wbgen2 from wrsw_pps_gen.wb
-  * Created        : Tue Nov 23 13:47:20 2010
+  * Author         : auto-generated by wbgen2 from ppsg-regs.wb
  * Standard       : ANSI C

-    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_pps_gen.wb
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE ppsg-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

 */

-#ifndef __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
-#define __WBGEN2_REGDEFS_WRSW_PPS_GEN_WB
+#ifndef __WBGEN2_REGDEFS_PPSG
+#define __WBGEN2_REGDEFS_PPSG

 #include <linux/types.h>


--- a/wbgen-regs/ppsg-regs.wb
+++ b/wbgen-regs/ppsg-regs.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+
+	 name = "WR Switch PPS generator and RTC";
+	 description = "Unit generating PPS signals and acting as a UTC real-time clock";
+	 hdl_entity = "pps_gen_wb";
+	 prefix = "ppsg";
+
+	 reg {
+			name = "Control Register";
+			prefix = "CR";
+			
+			field {
+				 name = "Reset counter";
+				 description = "write 1: resets the counter\
+                				write 0: no effect";
+
+				 prefix = "CNT_RST";
+				 type = MONOSTABLE;
+				 clock = "refclk_i";
+			};
+
+			field {
+				 name = "Enable counter";
+				 description = "1: PPS counter is enabled";
+
+				 prefix = "CNT_EN";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+				 clock = "refclk_i";
+			};
+
+			field {
+				 name = "Adjust offset";
+				 description = "write 1: Starts adjusting PPS/UTC offsets by adding the values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers to the current PPS counter value. These registers need to be programmed prior to update.\
+				                write 0: no effect\
+				 read 0: adjustment operation is done\
+				 read 1: adjustment operation is in progress";
+
+				 prefix = "CNT_ADJ";
+				 type = BIT;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_WRITE;
+				 load = LOAD_EXT;
+				 clock = "refclk_i";
+			};
+
+
+			field {
+				 name = "Set time";
+				 description = "write 1: Sets the UTC/PPS counter to values taken from ADJ_NSEC, ADJ_UTCLO, ADJ_UTCHI registers";
+				 prefix = "CNT_SET";
+				 type = MONOSTABLE;
+				 clock = "refclk_i";
+			};
+
+			field {
+				 name = "PPS Pulse width";
+				 description = "Width of generated PPS pulses in 125 MHz refernce clock cycles";
+				 prefix = "PWIDTH";
+				 size = 28;
+				 type = SLV;
+				 access_bus = READ_WRITE;
+				 access_dev = READ_ONLY;
+				 clock= "refclk_i";
+			 };
+		};
+
+		reg {
+			 name = "Nanosecond counter register";
+			 description = "Nanosecond part of current time, expressed as number of 125 MHz reference clock cycles";
+
+			 prefix = "CNTR_NSEC";
+			 field {
+					name = "Nanosecond counter";
+					type = SLV;
+					size = 28;
+					access_bus = READ_ONLY;
+					access_dev = WRITE_ONLY;
+					clock = "refclk_i";
+			 };
+
+		};
+
+		reg {
+			 name = "UTC Counter register (least-significant part)";
+			 description = "Lower 32 bits of current UTC time";
+
+			 prefix = "CNTR_UTCLO";
+			 field {
+					name = "UTC Counter";
+					type = SLV;
+					size = 32;
+					access_bus = READ_ONLY;
+					access_dev = WRITE_ONLY;
+					clock = "refclk_i";
+			 };
+		};
+
+		reg {
+			 name = "UTC Counter register (most-significant part)";
+			 description = "Highest 8 bits of current UTC time";
+
+			 prefix = "CNTR_UTCHI";
+			 field {
+					name = "UTC Counter";
+					type = SLV;
+					size = 8;
+					access_bus = READ_ONLY;
+					access_dev = WRITE_ONLY;
+					clock = "refclk_i";
+			 };
+		};
+
+	 reg {
+			name = "Nanosecond adjustment register";
+			description = "Adjustment value for nanosecond counter";
+
+			prefix = "ADJ_NSEC";
+			field {
+				 name = "Nanosecond adjustment";
+				 type = PASS_THROUGH;
+				 size = 28;
+			};
+	 };
+
+	 reg {
+			name = "UTC Adjustment register (least-significant part)";
+			description = "Lower 32 bits of adjustment value for UTC";
+
+			prefix = "ADJ_UTCLO";
+			field {
+				 name = "UTC Counter adjustment";
+				 type = PASS_THROUGH;
+				 size = 32;
+			};
+	 };
+
+
+	 reg {
+			name = "UTC Adjustment register (most-significant part)";
+			description = "Highest 8 bits of adjustment value for UTC";
+
+			prefix = "ADJ_UTCHI";
+			field {
+				 name = "UTC Counter adjustment";
+				 type = PASS_THROUGH;
+				 size = 8;
+			};
+	 };
+
+
+
+};
--- a/wbgen-regs/tstamp-regs.h
+++ b/wbgen-regs/tstamp-regs.h
@@ -2,17 +2,16 @@
  Register definitions for slave core: Shared TX Timestamping Unit (TXTSU)

  * File           : tstamp-regs.h
-  * Author         : auto-generated by wbgen2 from wrsw_txtsu.wb
-  * Created        : Tue Nov 23 13:47:20 2010
+  * Author         : auto-generated by wbgen2 from tstamp-regs.wb
  * Standard       : ANSI C

-    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wrsw_txtsu.wb
+    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE tstamp-regs.wb
    DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!

 */

-#ifndef __WBGEN2_REGDEFS_WRSW_TXTSU_WB
-#define __WBGEN2_REGDEFS_WRSW_TXTSU_WB
+#ifndef __WBGEN2_REGDEFS_TSTAMP
+#define __WBGEN2_REGDEFS_TSTAMP

 #include <linux/types.h>


--- a/wbgen-regs/tstamp-regs.wb
+++ b/wbgen-regs/tstamp-regs.wb
+-- -*- Mode: LUA; tab-width: 2 -*-
+
+peripheral {
+	 name = "Shared TX Timestamping Unit (TXTSU)";
+   prefix="txtsu";
+
+	 hdl_entity="wrsw_txtsu_wb";
+	 
+-- TXTSU shared FIFO
+
+	 fifo_reg {
+			size = 256; -- or more. We'll see :)
+			direction = CORE_TO_BUS;
+			prefix = "tsf";
+			name = "Timestamp FIFO";
+			description = "This FIFO holds the TX packet timestamps gathered from all switch endpoints. Each entry contains a single timestamp value consisting of 2 numbers:\
+			               - VAL_R - the timestamp taken at rising clock edge. This is the main timestamp value\
+            				 - VAL_F - few LSBs of timestamp taken at falling clock edge. It's used in conjunction with VAL_R to determine if the timestamp has been taken\
+                           		 properly (there was no metastability/setup/hold violation)\
+										 Entries also contain information required to identify the endpoint and frame for which the timestamp was taken:\
+                     - FID - Frame identifier assigned by the NIC\
+                     - PID - TXTSU port ID to which came the timestamp. Used to distinguish the timestamps for broadcast/multicast frames";
+
+			flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
+			flags_dev = {FIFO_FULL, FIFO_EMPTY};
+			
+			field {
+				 name = "Rising edge timestamp";
+				 descritpion = "Timestamp value taken on rising clock edge (full word)";
+				 prefix = "val_r";
+				 type = SLV;
+				 size = 28;
+			};
+
+			field {
+				 name = "Falling edge timestamp";
+				 description = "Timestamp value taken on falling clock edge (few LSBs)";
+				 prefix = "val_f";
+				 type = SLV;
+				 size = 4;
+			};
+
+
+			field {
+				 name ="Physical port ID";
+				 description = "Identifier of the TXTSU port to which came the timestamp. There may be multiple timestamps sharing the same FID value for broadcast/multicast packets.";
+				 prefix = "pid";
+				 type = SLV;
+				 size = 5;
+				 align= 16;
+			};
+		
+		
+			field {
+				 name = "Frame ID";
+				 description = "OOB Frame Identifier. Used to associate the timestamp value with transmitted packet.";
+				 prefix = "fid";
+				 type = SLV;
+				 size = 16;
+				 align = 16;
+		};
+	};
+
+-- TXTSU interrupts
+	irq {
+		 name = "TXTSU fifo not-empty";
+		 description = "Interrupt active when TXTSU shared FIFO contains any timestamps.";
+		 prefix = "nempty";
+		 trigger = LEVEL_0;
+	};
+
+};
\ No newline at end of file