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white-rabbit
wr-switch-sw
Commits
15257886
Commit
15257886
authored
Dec 05, 2014
by
Alessandro Rubini
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Merge branch 'at91-headers-cleanup'
parents
0be7fc94
98533745
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14 changed files
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73 additions
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7505 deletions
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build.sh
kernel/wr_rtu/build.sh
+0
-5
Makefile
userspace/Makefile
+0
-8
at91_pio.h
userspace/include/at91/at91_pio.h
+0
-49
at91_pmc.h
userspace/include/at91/at91_pmc.h
+0
-134
at91sam9263.h
userspace/include/at91/at91sam9263.h
+0
-127
at91sam9_smc.h
userspace/include/at91/at91sam9_smc.h
+0
-76
at91sam9g45.h
userspace/include/at91/at91sam9g45.h
+0
-7068
Makefile
userspace/libwr/Makefile
+19
-4
pio.h
userspace/libwr/include/libwr/pio.h
+1
-1
pio.c
userspace/libwr/pio.c
+3
-4
Makefile
userspace/snmpd/Makefile
+12
-2
Makefile
userspace/tools/Makefile
+2
-0
Makefile
userspace/wrsw_hal/Makefile
+17
-9
Makefile
userspace/wrsw_rtud/Makefile
+19
-18
No files found.
kernel/wr_rtu/build.sh
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0be7fc94
#!/bin/sh
.
../../../settings
make
CONFIG_DEBUG_SECTION_MISMATCH
=
y
ARCH
=
arm
CROSS_COMPILE
=
$CROSS_COMPILE_ARM
-C
../../../kernel
SUBDIRS
=
`
pwd
`
modules
$1
userspace/Makefile
View file @
15257886
# Most of the sub makefiles require some variables that used to be
# in the auto-generated ../Makedefs (when software was in svn).
# So let's add all of the needed variables here (environment can override)
ARCH
?=
arm
CROSS_COMPILE
?=
$(CROSS_COMPILE_ARM_PATH)$(CROSS_COMPILE_ARM_PREFIX)
CROSS_COMPILE_ARM
?=
$(CROSS_COMPILE)
# Installation of all of this stuff goes to images/wr in the output dir
WR_INSTALL_ROOT
?=
$(WRS_OUTPUT_DIR)
/images/wr
WRDEV_DIR
?=
$(WRS_BASE_DIR)
/..
...
...
userspace/include/at91/at91_pio.h
deleted
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0be7fc94
/*
* arch/arm/mach-at91/include/mach/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00
/* Enable Register */
#define PIO_PDR 0x04
/* Disable Register */
#define PIO_PSR 0x08
/* Status Register */
#define PIO_OER 0x10
/* Output Enable Register */
#define PIO_ODR 0x14
/* Output Disable Register */
#define PIO_OSR 0x18
/* Output Status Register */
#define PIO_IFER 0x20
/* Glitch Input Filter Enable */
#define PIO_IFDR 0x24
/* Glitch Input Filter Disable */
#define PIO_IFSR 0x28
/* Glitch Input Filter Status */
#define PIO_SODR 0x30
/* Set Output Data Register */
#define PIO_CODR 0x34
/* Clear Output Data Register */
#define PIO_ODSR 0x38
/* Output Data Status Register */
#define PIO_PDSR 0x3c
/* Pin Data Status Register */
#define PIO_IER 0x40
/* Interrupt Enable Register */
#define PIO_IDR 0x44
/* Interrupt Disable Register */
#define PIO_IMR 0x48
/* Interrupt Mask Register */
#define PIO_ISR 0x4c
/* Interrupt Status Register */
#define PIO_MDER 0x50
/* Multi-driver Enable Register */
#define PIO_MDDR 0x54
/* Multi-driver Disable Register */
#define PIO_MDSR 0x58
/* Multi-driver Status Register */
#define PIO_PUDR 0x60
/* Pull-up Disable Register */
#define PIO_PUER 0x64
/* Pull-up Enable Register */
#define PIO_PUSR 0x68
/* Pull-up Status Register */
#define PIO_ASR 0x70
/* Peripheral A Select Register */
#define PIO_BSR 0x74
/* Peripheral B Select Register */
#define PIO_ABSR 0x78
/* AB Status Register */
#define PIO_OWER 0xa0
/* Output Write Enable Register */
#define PIO_OWDR 0xa4
/* Output Write Disable Register */
#define PIO_OWSR 0xa8
/* Output Write Status Register */
#endif
userspace/include/at91/at91_pmc.h
deleted
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0be7fc94
/*
* arch/arm/mach-at91/include/mach/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC 0
#define AT91_PMC_SCER (AT91_PMC + 0x00)
/* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04)
/* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08)
/* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0)
/* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1)
/* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2)
/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91CAP9_PMC_DDR (1 << 2)
/* DDR Clock Enable [some SAM9 only] */
#define AT91RM9200_PMC_UHP (1 << 4)
/* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6)
/* USB Host Port Clock [AT91SAM926x only] */
#define AT91CAP9_PMC_UHP (1 << 6)
/* USB Host Port Clock [AT91CAP9 only] */
#define AT91SAM926x_PMC_UDP (1 << 7)
/* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8)
/* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9)
/* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10)
/* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11)
/* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16)
/* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17)
/* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10)
/* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14)
/* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18)
/* Peripheral Clock Status Register */
#define AT91_CKGR_UCKR (AT91_PMC + 0x1C)
/* UTMI Clock Register [some SAM9, CAP9] */
#define AT91_PMC_UPLLEN (1 << 16)
/* UTMI PLL Enable */
#define AT91_PMC_UPLLCOUNT (0xf << 20)
/* UTMI PLL Start-up Time */
#define AT91_PMC_BIASEN (1 << 24)
/* UTMI BIAS Enable */
#define AT91_PMC_BIASCOUNT (0xf << 28)
/* UTMI BIAS Start-up Time */
#define AT91_CKGR_MOR (AT91_PMC + 0x20)
/* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0)
/* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1)
/* Oscillator Bypass [SAM9x, CAP9] */
#define AT91_PMC_OSCOUNT (0xff << 8)
/* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24)
/* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0)
/* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16)
/* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28)
/* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c)
/* PLL B Register */
#define AT91_PMC_DIV (0xff << 0)
/* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8)
/* PLL Counter */
#define AT91_PMC_OUT (3 << 14)
/* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16)
/* PLL Multiplier */
#define AT91_PMC_USBDIV (3 << 28)
/* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28)
/* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30)
/* Master Clock Register */
#define AT91_PMC_CSS (3 << 0)
/* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_CSS_UPLL (3 << 0)
/* [some SAM9 only] */
#define AT91_PMC_PRES (7 << 2)
/* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8)
/* Master Clock Division */
#define AT91RM9200_PMC_MDIV_1 (0 << 8)
/* [AT91RM9200 only] */
#define AT91RM9200_PMC_MDIV_2 (1 << 8)
#define AT91RM9200_PMC_MDIV_3 (2 << 8)
#define AT91RM9200_PMC_MDIV_4 (3 << 8)
#define AT91SAM9_PMC_MDIV_1 (0 << 8)
/* [SAM9,CAP9 only] */
#define AT91SAM9_PMC_MDIV_2 (1 << 8)
#define AT91SAM9_PMC_MDIV_4 (2 << 8)
#define AT91SAM9_PMC_MDIV_6 (3 << 8)
/* [some SAM9 only] */
#define AT91SAM9_PMC_MDIV_3 (3 << 8)
/* [some SAM9 only] */
#define AT91_PMC_PDIV (1 << 12)
/* Processor Clock Division [some SAM9 only] */
#define AT91_PMC_PDIV_1 (0 << 12)
#define AT91_PMC_PDIV_2 (1 << 12)
#define AT91_PMC_PLLADIV2 (1 << 12)
/* PLLA divisor by 2 [some SAM9 only] */
#define AT91_PMC_PLLADIV2_OFF (0 << 12)
#define AT91_PMC_PLLADIV2_ON (1 << 12)
#define AT91_PMC_USB (AT91_PMC + 0x38)
/* USB Clock Register [some SAM9 only] */
#define AT91_PMC_USBS (0x1 << 0)
/* USB OHCI Input clock selection */
#define AT91_PMC_USBS_PLLA (0 << 0)
#define AT91_PMC_USBS_UPLL (1 << 0)
#define AT91_PMC_OHCIUSBDIV (0xF << 8)
/* Divider for USB OHCI Clock */
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4))
/* Programmable Clock 0-N Registers */
#define AT91_PMC_CSSMCK (0x1 << 8)
/* CSS or Master Clock Selection */
#define AT91_PMC_CSSMCK_CSS (0 << 8)
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER (AT91_PMC + 0x60)
/* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64)
/* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68)
/* Status Register */
#define AT91_PMC_MOSCS (1 << 0)
/* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1)
/* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2)
/* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3)
/* Master Clock */
#define AT91_PMC_LOCKU (1 << 6)
/* UPLL Lock [some SAM9, AT91CAP9 only] */
#define AT91_PMC_OSCSEL (1 << 7)
/* Slow Clock Oscillator [AT91CAP9 revC only] */
#define AT91_PMC_PCK0RDY (1 << 8)
/* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9)
/* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10)
/* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11)
/* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c)
/* Interrupt Mask Register */
#define AT91_PMC_PROT (AT91_PMC + 0xe4)
/* Protect Register [AT91CAP9 revC only] */
#define AT91_PMC_PROTKEY 0x504d4301
/* Activation Code */
#define AT91_PMC_VER (AT91_PMC + 0xfc)
/* PMC Module Version [AT91CAP9 only] */
#endif
userspace/include/at91/at91sam9263.h
deleted
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0be7fc94
/*
* arch/arm/mach-at91/include/mach/at91sam9263.h
*
* (C) 2007 Atmel Corporation.
*
* Common definitions.
* Based on AT91SAM9263 datasheet revision B (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9263_H
#define AT91SAM9263_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0
/* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1
/* System Peripherals */
#define AT91SAM9263_ID_PIOA 2
/* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3
/* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4
/* Parallel IO Controller C, D and E */
#define AT91SAM9263_ID_US0 7
/* USART 0 */
#define AT91SAM9263_ID_US1 8
/* USART 1 */
#define AT91SAM9263_ID_US2 9
/* USART 2 */
#define AT91SAM9263_ID_MCI0 10
/* Multimedia Card Interface 0 */
#define AT91SAM9263_ID_MCI1 11
/* Multimedia Card Interface 1 */
#define AT91SAM9263_ID_CAN 12
/* CAN */
#define AT91SAM9263_ID_TWI 13
/* Two-Wire Interface */
#define AT91SAM9263_ID_SPI0 14
/* Serial Peripheral Interface 0 */
#define AT91SAM9263_ID_SPI1 15
/* Serial Peripheral Interface 1 */
#define AT91SAM9263_ID_SSC0 16
/* Serial Synchronous Controller 0 */
#define AT91SAM9263_ID_SSC1 17
/* Serial Synchronous Controller 1 */
#define AT91SAM9263_ID_AC97C 18
/* AC97 Controller */
#define AT91SAM9263_ID_TCB 19
/* Timer Counter 0, 1 and 2 */
#define AT91SAM9263_ID_PWMC 20
/* Pulse Width Modulation Controller */
#define AT91SAM9263_ID_EMAC 21
/* Ethernet */
#define AT91SAM9263_ID_2DGE 23
/* 2D Graphic Engine */
#define AT91SAM9263_ID_UDP 24
/* USB Device Port */
#define AT91SAM9263_ID_ISI 25
/* Image Sensor Interface */
#define AT91SAM9263_ID_LCDC 26
/* LCD Controller */
#define AT91SAM9263_ID_DMA 27
/* DMA Controller */
#define AT91SAM9263_ID_UHP 29
/* USB Host port */
#define AT91SAM9263_ID_IRQ0 30
/* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9263_ID_IRQ1 31
/* Advanced Interrupt Controller (IRQ1) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9263_BASE_UDP 0xfff78000
#define AT91SAM9263_BASE_TCB0 0xfff7c000
#define AT91SAM9263_BASE_TC0 0xfff7c000
#define AT91SAM9263_BASE_TC1 0xfff7c040
#define AT91SAM9263_BASE_TC2 0xfff7c080
#define AT91SAM9263_BASE_MCI0 0xfff80000
#define AT91SAM9263_BASE_MCI1 0xfff84000
#define AT91SAM9263_BASE_TWI 0xfff88000
#define AT91SAM9263_BASE_US0 0xfff8c000
#define AT91SAM9263_BASE_US1 0xfff90000
#define AT91SAM9263_BASE_US2 0xfff94000
#define AT91SAM9263_BASE_SSC0 0xfff98000
#define AT91SAM9263_BASE_SSC1 0xfff9c000
#define AT91SAM9263_BASE_AC97C 0xfffa0000
#define AT91SAM9263_BASE_SPI0 0xfffa4000
#define AT91SAM9263_BASE_SPI1 0xfffa8000
#define AT91SAM9263_BASE_CAN 0xfffac000
#define AT91SAM9263_BASE_PWMC 0xfffb8000
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
#define AT91_BASE_SYS 0xffffe000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
#define AT91_SMC0 (0xffffe400 - AT91_BASE_SYS)
#define AT91_ECC1 (0xffffe600 - AT91_BASE_SYS)
#define AT91_SDRAMC1 (0xffffe800 - AT91_BASE_SYS)
#define AT91_SMC1 (0xffffea00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffed10 - AT91_BASE_SYS)
#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
#define AT91_PIOE (0xfffffa00 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT0 (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_RTT1 (0xfffffd50 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS)
#define AT91_USART0 AT91SAM9263_BASE_US0
#define AT91_USART1 AT91SAM9263_BASE_US1
#define AT91_USART2 AT91SAM9263_BASE_US2
#define AT91_SMC AT91_SMC0
/*
* Internal Memory.
*/
#define AT91SAM9263_SRAM0_BASE 0x00300000
/* Internal SRAM 0 base address */
#define AT91SAM9263_SRAM0_SIZE (80 * SZ_1K)
/* Internal SRAM 0 size (80Kb) */
#define AT91SAM9263_ROM_BASE 0x00400000
/* Internal ROM base address */
#define AT91SAM9263_ROM_SIZE SZ_128K
/* Internal ROM size (128Kb) */
#define AT91SAM9263_SRAM1_BASE 0x00500000
/* Internal SRAM 1 base address */
#define AT91SAM9263_SRAM1_SIZE SZ_16K
/* Internal SRAM 1 size (16Kb) */
#define AT91SAM9263_LCDC_BASE 0x00700000
/* LCD Controller */
#define AT91SAM9263_DMAC_BASE 0x00800000
/* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000
/* USB Host controller */
#endif
userspace/include/at91/at91sam9_smc.h
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0be7fc94
/*
* arch/arm/mach-at91/include/mach/at91sam9_smc.h
*
* Copyright (C) 2007 Andrew Victor
* Copyright (C) 2007 Atmel Corporation.
*
* Static Memory Controllers (SMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10))
/* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0)
/* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8)
/* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16)
/* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24)
/* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10))
/* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0)
/* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8)
/* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16)
/* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24)
/* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10))
/* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 )
/* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16)
/* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10))
/* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0)
/* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1)
/* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 4)
/* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 4)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 4)
#define AT91_SMC_EXNWMODE_READY (3 << 4)
#define AT91_SMC_BAT (1 << 8)
/* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12)
/* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16)
/* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20)
/* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24)
/* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28)
/* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#if defined(AT91_SMC1)
/* The AT91SAM9263 has 2 Static Memory contollers */
#define AT91_SMC1_SETUP(n) (AT91_SMC1 + 0x00 + ((n)*0x10))
/* Setup Register for CS n */
#define AT91_SMC1_PULSE(n) (AT91_SMC1 + 0x04 + ((n)*0x10))
/* Pulse Register for CS n */
#define AT91_SMC1_CYCLE(n) (AT91_SMC1 + 0x08 + ((n)*0x10))
/* Cycle Register for CS n */
#define AT91_SMC1_MODE(n) (AT91_SMC1 + 0x0c + ((n)*0x10))
/* Mode Register for CS n */
#endif
#endif
userspace/include/at91/at91sam9g45.h
deleted
100644 → 0
View file @
0be7fc94
This diff is collapsed.
Click to expand it.
userspace/libwr/Makefile
View file @
15257886
CC
=
$(CROSS_COMPILE)
gcc
AR
=
$(CROSS_COMPILE)
ar
CFLAGS
=
-Wall
-I
.
-O2
-DDEBUG
-ggdb
-I
./include
-I
../include
-I
../mini-rpc
OBJS
=
trace.o init.o fpga_io.o util.o pps_gen.o i2c.o shw_io.o i2c_bitbang.o
\
i2c_fpga_reg.o pio.o libshw_i2c.o i2c_sfp.o fan.o i2c_io.o hwiu.o
\
ptpd_netif.o hal_client.o
\
...
...
@@ -9,6 +5,25 @@ OBJS = trace.o init.o fpga_io.o util.o pps_gen.o i2c.o shw_io.o i2c_bitbang.o \
LIB
=
libwr.a
WR_INSTALL_ROOT
?=
/usr/lib/white-rabbit
# # Standard stanza for cross-compilation (courtesy of the linux makefile)
AS
=
$(CROSS_COMPILE)
as
LD
=
$(CROSS_COMPILE)
ld
CC
=
$(CROSS_COMPILE)
gcc
CPP
=
$(CC)
-E
AR
=
$(CROSS_COMPILE)
ar
NM
=
$(CROSS_COMPILE)
nm
STRIP
=
$(CROSS_COMPILE)
strip
OBJCOPY
=
$(CROSS_COMPILE)
objcopy
OBJDUMP
=
$(CROSS_COMPILE)
objdump
CFLAGS
=
-Wall
-I
.
-O2
-DDEBUG
-ggdb
\
-I
./include
\
-I
../include
\
-I
../mini-rpc
\
-I
$(LINUX)
/arch/arm/mach-at91/include
all
:
$(LIB)
$(LIB)
:
$(OBJS)
...
...
userspace/libwr/include/libwr/pio.h
View file @
15257886
...
...
@@ -3,7 +3,7 @@
#include <stdint.h>
#include <
at91
/at91_pio.h>
#include <
mach
/at91_pio.h>
#define NUM_PIO_BANKS 6
...
...
userspace/libwr/pio.c
View file @
15257886
...
...
@@ -6,9 +6,8 @@
#include <inttypes.h>
#include <fcntl.h>
#include <at91/at91sam9g45.h>
#include <at91/at91_pmc.h>
#include <at91/at91_pio.h>
#include <mach/at91_pmc.h>
#include <mach/at91_pio.h>
#include <libwr/pio.h>
#include <libwr/trace.h>
...
...
@@ -44,7 +43,7 @@ int shw_pio_mmap_init()
_sys_base
=
mmap
(
NULL
,
0x4000
,
PROT_READ
|
PROT_WRITE
,
MAP_SHARED
,
fd
,
(
off_t
)
AT91C_BASE_SYS
);
AT91C_BASE_SYS_RAW
);
if
(
_sys_base
==
NULL
)
{
TRACE
(
TRACE_FATAL
,
"can't mmap CPU GPIO regs"
);
...
...
userspace/snmpd/Makefile
View file @
15257886
...
...
@@ -4,8 +4,18 @@ SNMP_BUILD := $(wildcard $(SNMP_BUILD)/output/build/netsnmp-*)
NET_SNMP_CONFIG
?=
$(SNMP_BUILD)
/net-snmp-config
CC
=
$(CROSS_COMPILE)
gcc
LD
=
$(CROSS_COMPILE)
ld
WR_INSTALL_ROOT
?=
/usr/lib/white-rabbit
# # Standard stanza for cross-compilation (courtesy of the linux makefile)
AS
=
$(CROSS_COMPILE)
as
LD
=
$(CROSS_COMPILE)
ld
CC
=
$(CROSS_COMPILE)
gcc
CPP
=
$(CC)
-E
AR
=
$(CROSS_COMPILE)
ar
NM
=
$(CROSS_COMPILE)
nm
STRIP
=
$(CROSS_COMPILE)
strip
OBJCOPY
=
$(CROSS_COMPILE)
objcopy
OBJDUMP
=
$(CROSS_COMPILE)
objdump
# defer running "net-snmp-config --cflags" so it is visible in make output
CFLAGS
+=
-fPIC
-Wall
$$
(
$(NET_SNMP_CONFIG)
--cflags
|
sed
s,-I/usr/include,,
)
...
...
userspace/tools/Makefile
View file @
15257886
...
...
@@ -5,6 +5,8 @@ TOOLS += wrs_vlans wrs_dump_shmem
TOOLS
+=
sdb-read
TOOLS
+=
nbtee
WR_INSTALL_ROOT
?=
/usr/lib/white-rabbit
# # Standard stanza for cross-compilation (courtesy of the linux makefile)
AS
=
$(CROSS_COMPILE)
as
...
...
userspace/wrsw_hal/Makefile
View file @
15257886
CC
=
$(CROSS_COMPILE)
gcc
OBJS
=
hal_exports.o hal_main.o hal_ports.o hal_config.o hal_timing.o
BINARY
=
wrsw_hal
# We must include stuff from wr_ipc, which is installed.
# If this is build under build scripts, it's $WRS_OUTPUT_DIR/images/wr
WR_INSTALL_ROOT
?=
/usr/lib/white-rabbit
WR_INCLUDE
=
$(WR_INSTALL_ROOT)
/include
WR_LIB
=
$(WR_INSTALL_ROOT)
/lib
CFLAGS
=
-O
-g
-Wall
-I
../include
-I
../libwr/include
-I
../mini-rpc
-I
$(WR_INCLUDE)
# # Standard stanza for cross-compilation (courtesy of the linux makefile)
AS
=
$(CROSS_COMPILE)
as
LD
=
$(CROSS_COMPILE)
ld
CC
=
$(CROSS_COMPILE)
gcc
CPP
=
$(CC)
-E
AR
=
$(CROSS_COMPILE)
ar
NM
=
$(CROSS_COMPILE)
nm
STRIP
=
$(CROSS_COMPILE)
strip
OBJCOPY
=
$(CROSS_COMPILE)
objcopy
OBJDUMP
=
$(CROSS_COMPILE)
objdump
CFLAGS
=
-O
-g
-Wall
\
-I
../include
\
-I
../libwr/include
\
-I
../mini-rpc
\
-I
$(LINUX)
/arch/arm/mach-at91/include
ifdef
WRS_HAL_DEBUG
CFLAGS
+=
-DDEBUG
...
...
@@ -26,9 +35,8 @@ $(BINARY): $(OBJS)
$(CC)
-o
$@
$^
$(LDFLAGS)
install
:
all
install
-d
$(WR_INSTALL_ROOT)
/bin
$(WR_INSTALL_ROOT)
/include
install
-d
$(WR_INSTALL_ROOT)
/bin
install
$(BINARY)
$(WR_INSTALL_ROOT)
/bin
install
../include/hal/hal_exports.h wrsw_hal.h
$(WR_INSTALL_ROOT)
/include
clean
:
rm
-f
$(BINARY)
*
.o
*
~
userspace/wrsw_rtud/Makefile
View file @
15257886
...
...
@@ -4,39 +4,40 @@ SRCFILES = mac.c rtu_drv.c rtu_ext_drv.c rtu_hash.c rtu_fd.c rtud.c \
rtud_exports.c utils.c
OBJFILES
=
$
(
patsubst %.c,%.o,
$(SRCFILES)
)
CC
=
$(CROSS_COMPILE)
gcc
# We must include stuff from various headers, which are installed.
# If this is build under build scripts, it's $WRS_OUTPUT_DIR/images/wr
WR_INSTALL_ROOT
?=
/usr/lib/white-rabbit
WR_INCLUDE
=
$(WR_INSTALL_ROOT)
/include
WR_LIB
=
$(WR_INSTALL_ROOT)
/lib
CFLAGS
=
-O2
-Wall
-ggdb
\
-I
../mini-rpc
-I
../include
-I
../libwr/include
\
-I
$(WR_INCLUDE)
-I
$(LINUX)
/include
# -I$(CROSS_COMPILE_ARM_PATH)/../include
# # Standard stanza for cross-compilation (courtesy of the linux makefile)
AS
=
$(CROSS_COMPILE)
as
LD
=
$(CROSS_COMPILE)
ld
CC
=
$(CROSS_COMPILE)
gcc
CPP
=
$(CC)
-E
AR
=
$(CROSS_COMPILE)
ar
NM
=
$(CROSS_COMPILE)
nm
STRIP
=
$(CROSS_COMPILE)
strip
OBJCOPY
=
$(CROSS_COMPILE)
objcopy
OBJDUMP
=
$(CROSS_COMPILE)
objdump
CFLAGS
=
-O2
-Wall
-ggdb
\
-I
../mini-rpc
\
-I
../include
\
-I
../libwr/include
\
-I
$(LINUX)
/arch/arm/mach-at91/include
ifdef
WRS_RTUD_DEBUG
CFLAGS
+=
-DDEBUG
endif
LDFLAGS
:=
-L
../libwr
-L
../mini-rpc
\
-lwr
-lpthread
-lminipc
RM
:=
rm
-f
.PHONY
:
all
all
:
$(PROGRAM)
$(PROGRAM)
:
$(OBJFILES)
$(CC)
-o
$@
$(OBJFILES)
$(LDFLAGS)
clean
:
$(RM)
$(PROGRAM)
$(OBJFILES)
rm
-f
$(PROGRAM)
*
.o
*
~
install
:
all
cp
$(PROGRAM)
$(WR_INSTALL_ROOT)
/bin
install
-d
$(WR_INSTALL_ROOT)
/bin
install
$(PROGRAM)
$(WR_INSTALL_ROOT)
/bin
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