wrsw_rtu: re-done Wishbone register layout to have indirect addressing of PCR registers. Replaced plain signal WB register connections with a structure

swcore[new mpm]: bugfix in the MPM: empty HIGH at the very last word caused the Rx Path to go nuts, fixed by ANDing d_last_int with counter_equals

swcore[new mpm]: corrected the way the first page is cleared and how we make sure that it is cleared at the end of the first page receptipn

swcore[new mpm]: more debugging and corrections of input block, changing simulatioon to test 16 ports

RTU: added optional hack (can be turned on with generics) which was introduce to prevent Endpoint from pushing new requests to RTU while the current one is currently handled. This might cause errors in forwaring packets (RTU handling requets of packets which were dropped by Endpint because the buffer has become full waiting for decisions of RTU of the previous packets. Everythig because RTU is to slow .... (testing throwing bursts of frames at 14 ports simultaneusly). Also: added missing prioriy connection in the wrapper

RTU: modified the WB interface of RTU to extend the number of ports supported by rtu (it was up to 10). Now, WB-wise RTU supports 20 ports (however, there are other limitations which make the current max number of ports = 16)

swcore[new mpm]: input/output blocks debugged (output block still needs few more features and performance boost

swcore[new mpm]: revised input block. I reanalized the FSMs (we have 4 there) and improved the synchronization between them, cleaned the code, etc. Needs more debugging. At this stage, code passes simple test