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wr-switch-hdl
Commit d19e76c3 authored by Maciej Lipinski's avatar Maciej Lipinski
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swcore: added resource manager, handling in input_block not implemented yet

parent 68b4150b
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Showing with 453 additions and 158 deletions
modules/wrsw_shared_types_pkg.vhd
View file @ d19e76c3
......@@ -25,4 +25,5 @@ package wrsw_shared_types_pkg is
type t_rtu_request_array is array(integer range <>) of t_rtu_request;
type t_rtu_response_array is array(integer range <>) of t_rtu_response;
end wrsw_shared_types_pkg;
modules/wrsw_swcore/Manifest.py
View file @ d19e76c3
......@@ -18,6 +18,8 @@ files = [
"old_allocator/swc_multiport_page_allocator.vhd",
"old_allocator/swc_page_alloc_old.vhd",
"swc_alloc_resource_manager.vhd",
#"swc_multiport_page_allocator.vhd",
#"swc_page_alloc_old.vhd",
......
modules/wrsw_swcore/swc_ll_read_data_validation.vhd
View file @ d19e76c3
......@@ -114,7 +114,7 @@ begin
-- the data being written to the Linked List DPRAM is what we are wating for and it's valid.
valid_data_write <= '1' when (read_addr_i = write_addr_i and write_data_valid_i = '1' and write_data_ready_i = '1') else '0';
process(clk_i, rst_n_i)
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
......
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ d19e76c3
......@@ -89,10 +89,17 @@ package swc_swcore_pkg is
component swc_page_allocator
generic (
g_num_pages : integer;
g_page_addr_width : integer;
g_num_ports : integer;
g_usecount_width : integer);
g_num_pages : integer;
g_page_addr_width : integer;
g_num_ports : integer;
g_usecount_width : integer;
--- management
g_page_size : integer := 64;
g_max_pck_size : integer := 759;
g_special_res_num_pages : integer := 256;
g_resource_num : integer := 3;
g_resource_num_width : integer := 2
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -107,7 +114,15 @@ package swc_swcore_pkg is
free_last_usecnt_o : out std_logic;
idle_o : out std_logic;
done_o : out std_logic;
nomem_o : out std_logic);
nomem_o : out std_logic;
resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
free_resource_valid_i : in std_logic;
rescnt_page_num_i : in std_logic_vector(g_page_addr_width -1 downto 0);
res_full_o : out std_logic_vector(g_resource_num -1 downto 0);
res_almost_full_o : out std_logic_vector(g_resource_num -1 downto 0)
);
end component;
--component swc_page_allocator
......@@ -190,7 +205,10 @@ package swc_swcore_pkg is
g_page_size : integer ;
g_partial_select_width : integer ;
g_ll_data_width : integer ;
g_port_index : integer
g_port_index : integer ;
--- resource management
g_resource_num : integer;
g_resource_num_width : integer
);
port (
clk_i : in std_logic;
......@@ -211,6 +229,15 @@ package swc_swcore_pkg is
mmu_usecnt_o : out std_logic_vector(g_usecount_width - 1 downto 0);
mmu_nomem_i : in std_logic;
--- management
mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
mmu_resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
mmu_free_resource_valid_o : out std_logic;
mmu_rescnt_page_num_o : out std_logic_vector(g_page_addr_width-1 downto 0);
mmu_res_almost_full_i : in std_logic_vector(g_resource_num -1 downto 0);
mmu_res_full_i : in std_logic_vector(g_resource_num -1 downto 0);
rtu_rsp_valid_i : in std_logic;
rtu_rsp_ack_o : out std_logic;
rtu_dst_port_mask_i : in std_logic_vector(g_num_ports - 1 downto 0);
......@@ -248,7 +275,13 @@ package swc_swcore_pkg is
g_page_addr_width : integer ;--:= c_swc_page_addr_width;
g_num_ports : integer ;--:= c_swc_num_ports
g_page_num : integer ;--:= c_swc_packet_mem_num_pages
g_usecount_width : integer --:= c_swc_usecount_width
g_usecount_width : integer ;--:= c_swc_usecount_width
--- resource manager
g_max_pck_size : integer ;
g_page_size : integer ;
g_special_res_num_pages : integer ;
g_resource_num : integer ; -- this include 1 for unknown
g_resource_num_width : integer
);
port (
rst_n_i : in std_logic;
......@@ -264,11 +297,16 @@ package swc_swcore_pkg is
pgaddr_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
pgaddr_force_free_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
pgaddr_usecnt_i : in std_logic_vector(g_num_ports * g_page_addr_width - 1 downto 0);
usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
usecnt_i : in std_logic_vector(g_num_ports * g_usecount_width - 1 downto 0);
pgaddr_alloc_o : out std_logic_vector(g_page_addr_width-1 downto 0);
free_last_usecnt_o : out std_logic_vector(g_num_ports - 1 downto 0);
nomem_o : out std_logic
-- tap_out_o :out std_logic_vector(62 + 49 downto 0)
nomem_o : out std_logic;
resource_i : in std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
resource_o : out std_logic_vector(g_num_ports * g_resource_num_width-1 downto 0);
free_resource_valid_i : in std_logic_vector(g_num_ports - 1 downto 0);
rescnt_page_num_i : in std_logic_vector(g_num_ports * g_page_addr_width-1 downto 0);
res_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0);
res_almost_full_o : out std_logic_vector(g_num_ports * g_resource_num -1 downto 0)
);
end component;
......@@ -542,10 +580,34 @@ component swc_multiport_pck_pg_free_module is
write_data_valid_i : in std_logic;
write_data_ready_i : in std_logic;
read_data_o : out std_logic_vector(g_data_width - 1 downto 0);
read_data_valid_o : out std_logic
read_data_o : out std_logic_vector(g_data_width - 1 downto 0);
read_data_valid_o : out std_logic
);
end component;
component swc_alloc_resource_manager is
generic (
g_num_ports : integer ;
g_max_pck_size : integer;
g_page_size : integer;
g_total_num_pages : integer := 2048;
g_total_num_pages_width : integer := 11;
g_special_res_num_pages : integer := 248;
g_resource_num : integer := 3; -- this include 1 for unknown
g_resource_num_width : integer := 2
);
port (
clk_i : in std_logic; -- clock & reset
rst_n_i : in std_logic;
resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
alloc_i : in std_logic;
free_i : in std_logic;
rescnt_set_i : in std_logic;
rescnt_page_num_i : in std_logic_vector(g_total_num_pages_width-1 downto 0);
res_full_o : out std_logic_vector(g_resource_num- 1 downto 0);
res_almost_full_o : out std_logic_vector(g_resource_num- 1 downto 0)
);
end component;
function f_sel2partialSel(sel : std_logic_vector; partialSelWidth: integer) return std_logic_vector;
function f_partialSel2sel(partialSel: std_logic_vector; selWidth : integer) return std_logic_vector;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ d19e76c3
......@@ -57,7 +57,7 @@ entity xswc_core is
generic(
g_prio_num : integer ;--:= c_swc_output_prio_num; [works only for value of 8, output_block-causes problem]
g_max_pck_size : integer ;--:= c_swc_max_pck_size
g_max_pck_size : integer ;-- in 16bits words --:= c_swc_max_pck_size
g_max_oob_size : integer ;
g_num_ports : integer ;--:= c_swc_num_ports
g_pck_pg_free_fifo_size : integer ; --:= c_swc_freeing_fifo_size (in pck_pg_free_module.vhd)
......@@ -69,8 +69,8 @@ entity xswc_core is
g_wb_addr_width : integer ;
g_wb_sel_width : integer ;
g_wb_ob_ignore_ack : boolean := true ;
g_mpm_mem_size : integer ;
g_mpm_page_size : integer ;
g_mpm_mem_size : integer ; -- in 16bits words
g_mpm_page_size : integer ; -- in 16bits words
g_mpm_ratio : integer ;
g_mpm_fifo_size : integer ;
g_mpm_fetch_next_pg_in_advance : boolean
......@@ -116,10 +116,16 @@ architecture rtl of xswc_core is
constant c_mpm_partial_sel_width : integer := integer(g_wb_sel_width-1);
constant c_mpm_page_size_width : integer := integer(CEIL(LOG2(real(g_mpm_page_size-1))));
constant c_ll_addr_width : integer := c_mpm_page_addr_width;
constant c_ll_data_width : integer := c_mpm_page_addr_width + c_max_oob_size_width + 3;
-- resource management -----------------------
constant c_res_mmu_max_pck_size : integer := 759; -- in 16 bit words (1518 [octets])/(2 [octets])
constant c_res_mmu_special_res_num_pages : integer := 256;
constant c_res_mmu_resource_num : integer := 3; -- (1) unknown; (2) special; (3) normal
constant c_res_mmu_resource_num_width : integer := 2;
----------------------------------------------
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block<< with >>Memory Management Unit<<
----------------------------------------------------------------------------------------------------
......@@ -291,6 +297,19 @@ architecture rtl of xswc_core is
signal CONTROL0 : std_logic_vector(35 downto 0);
signal tap : std_logic_vector(127 downto 0);
----------------------------------------------------------------------------------------------------
-- signals connecting >>Input Block (IB) << with >>Page allocator (MMU)<< -- resource management
----------------------------------------------------------------------------------------------------
signal mmu2ib_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
signal ib2mmu_resource : std_logic_vector(g_num_ports*c_res_mmu_resource_num_width -1 downto 0);
signal ib2mmu_free_resource_valid : std_logic_vector(g_num_ports -1 downto 0);
signal ib2mmu_rescnt_page_num : std_logic_vector(g_num_ports*c_mpm_page_addr_width -1 downto 0);
signal mmu2ib_res_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
signal mmu2ib_res_almost_full : std_logic_vector(g_num_ports*c_res_mmu_resource_num -1 downto 0);
begin --rtl
--chipscope_icon_1: chipscope_icon
......@@ -324,7 +343,10 @@ architecture rtl of xswc_core is
g_page_size => g_mpm_page_size,
g_partial_select_width => c_mpm_partial_sel_width,
g_ll_data_width => c_ll_data_width,
g_port_index => i
g_port_index => i,
-- resource management
g_resource_num => c_res_mmu_resource_num,
g_resource_num_width => c_res_mmu_resource_num_width
)
port map (
clk_i => clk_i,
......@@ -349,6 +371,14 @@ architecture rtl of xswc_core is
mmu_nomem_i => mmu_nomem,
mmu_pageaddr_o => ib_pageaddr_output((i + 1) * c_mpm_page_addr_width - 1 downto i * c_mpm_page_addr_width),
-- resource management
mmu_resource_i => mmu2ib_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
mmu_resource_o => ib2mmu_resource ((i+1)*c_res_mmu_resource_num_width -1 downto i*c_res_mmu_resource_num_width),
mmu_free_resource_valid_o=> ib2mmu_free_resource_valid(i),
mmu_rescnt_page_num_o => ib2mmu_rescnt_page_num ((i+1)*c_mpm_page_addr_width -1 downto i*c_mpm_page_addr_width),
mmu_res_full_i => mmu2ib_res_full ((i+1)*c_res_mmu_resource_num -1 downto i*c_res_mmu_resource_num),
mmu_res_almost_full_i => mmu2ib_res_almost_full ((i+1)*c_res_mmu_resource_num -1 downto i*c_res_mmu_resource_num),
-------------------------------------------------------------------------------
-- I/F with Pck's Pages Freeing Module (PPFM)
-------------------------------------------------------------------------------
......@@ -544,7 +574,13 @@ architecture rtl of xswc_core is
g_page_addr_width => c_mpm_page_addr_width,
g_num_ports => g_num_ports,
g_page_num => c_mpm_page_num,
g_usecount_width => c_usecount_width
g_usecount_width => c_usecount_width,
-- management
g_max_pck_size => c_res_mmu_max_pck_size,
g_page_size => g_mpm_page_size,
g_special_res_num_pages => c_res_mmu_special_res_num_pages,
g_resource_num => c_res_mmu_resource_num,
g_resource_num_width => c_res_mmu_resource_num_width
)
port map (
rst_n_i => rst_n_i,
......@@ -568,8 +604,15 @@ architecture rtl of xswc_core is
force_free_done_o => mmu_force_free_done,
pgaddr_force_free_i => ppfm_force_free_pgaddr,
nomem_o => mmu_nomem
nomem_o => mmu_nomem,
--------------------------- resource management ----------------------------------
resource_i => ib2mmu_resource,
resource_o => mmu2ib_resource,
free_resource_valid_i => ib2mmu_free_resource_valid,
rescnt_page_num_i => ib2mmu_rescnt_page_num,
res_full_o => mmu2ib_res_full,
res_almost_full_o => mmu2ib_res_almost_full
-- tap_out_o => tap_alloc
);
......
modules/wrsw_swcore/xswc_input_block.vhd
View file @ d19e76c3
......@@ -113,7 +113,12 @@ entity xswc_input_block is
g_partial_select_width : integer;
g_ll_data_width : integer;
g_max_oob_size : integer; -- on words (16 bits)
g_port_index : integer -- ID of this port
g_port_index : integer; -- ID of this port
--- resource management
g_resource_num : integer;
g_resource_num_width : integer
);
port (
clk_i : in std_logic;
......@@ -160,6 +165,24 @@ entity xswc_input_block is
-- memory full
mmu_nomem_i : in std_logic;
--------------------------- resource management ----------------------------------
-- resource number
mmu_resource_i : in std_logic_vector(g_resource_num_width-1 downto 0);
-- outputed when freeing
mmu_resource_o : out std_logic_vector(g_resource_num_width-1 downto 0);
-- used only when freeing page,
-- if HIGH then the input resource_i value will be used
-- if LOW then the value read from memory will be used (stored along with usecnt)
mmu_free_resource_valid_o : out std_logic;
-- number of pages added to the resurce
mmu_rescnt_page_num_o : out std_logic_vector(g_page_addr_width-1 downto 0);
mmu_res_full_i : in std_logic_vector(g_resource_num -1 downto 0);
mmu_res_almost_full_i : in std_logic_vector(g_resource_num -1 downto 0);
-------------------------------------------------------------------------------
-- I/F with Routing Table Unit (RTU)
-------------------------------------------------------------------------------
......@@ -2041,4 +2064,12 @@ tap_out_o <= f_slv_resize( --
mpm_pg_req_i, -- 16
50 + 62);
------------------ resource management -----------------------------
mmu_rescnt_page_num_o <= (others => '0');
mmu_free_resource_valid_o <= '0';
mmu_resource_o <= (others => '0');
end syn; -- arch
testbench/swcore/allocator/common.svh
View file @ d19e76c3
......@@ -219,6 +219,7 @@ interface IAllocatorPort (input clk_i);
endinterface // IAllocatorPort
`ifdef dupa1234
typedef virtual IAllocatorPort VIAllocatorPort;
task automatic execute_requests(VIAllocatorPort port, ref alloc_request_t rqs[$], input int verbose =0);
......@@ -272,3 +273,4 @@ task automatic execute_requests(VIAllocatorPort port, ref alloc_request_t rqs[$]
endcase // case (rqs[i].t)
end
endtask // execute_requests
`endif
\ No newline at end of file
testbench/swcore/swc_core_generic.sv
View file @ d19e76c3
......@@ -57,7 +57,7 @@
`include "allocator/common.svh"
//`define DBG_ALLOC //if defined, the allocation debugging is active: we track the number of allocated
`define DBG_ALLOC //if defined, the allocation debugging is active: we track the number of allocated
//and de-allocated pages
typedef struct {
......@@ -229,8 +229,12 @@ module main_generic;
// end
// begin
// automatic int tmp_rtu_wait = (77*((global_seed*100)/3))%400 ;
wait_cycles(tmp_rtu_wait);
$display("rtu wait: %4d cycles",tmp_rtu_wait);
//wait_cycles(tmp_rtu_wait);
//$display("rtu wait: %4d cycles",tmp_rtu_wait);
set_rtu_rsp(port,1 /*valid*/,drop /*drop*/,prio /*prio*/,mask /*mask*/);
// end
// join
......@@ -425,7 +429,7 @@ module main_generic;
int j;
int n_ports = `c_num_ports;
int mask_opt=1;
int n_packets =500;
int n_packets =50; //200
// initialization
initPckSrcAndSink(src, sink, n_ports);
gen = new;
......@@ -441,7 +445,7 @@ module main_generic;
//for(j=0;j<`c_num_ports;j++) begin
//U_wrf_sink[0].permanent_stall_enable();
//U_wrf_sink[1].permanent_stall_enable();
//////////////////////////////////////////////////////////////////////////////////////////////////
......@@ -644,11 +648,11 @@ module main_generic;
*/
`define MMU DUT_xswcore_wrapper.DUT_swc_core.xswcore.memory_management_unit
`define MMU DUT_xswcore_wrapper.DUT_swc_core.xswcore.memory_management_unit
`define MMUC DUT_xswcore_wrapper.DUT_swc_core.xswcore.memory_management_unit.alloc_core
wait_cycles(1000);
// U_wrf_sink[0].permanent_stall_disable();
wait_cycles(70000);
U_wrf_sink[1].permanent_stall_disable();
wait_cycles(40000);
......
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