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wr-switch-hdl
Commit c153df5b authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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wrsw_swcore: bugfix: MPM ReadPath -> LL moved to IO clock domain

parent 84500045
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Showing with 15 additions and 24 deletions
modules/wrsw_swcore/mpm/mpm_read_path.vhd
View file @ c153df5b
......@@ -312,25 +312,17 @@ begin -- rtl
p_ll_mux_addr : process(clk_io_i)
-- ML
--variable muxed : std_logic_vector(g_page_addr_width-1 downto 0);
-- ML
variable muxed : std_logic_vector(g_page_addr_width-1 downto 0);
begin
if rising_edge(clk_io_i) then
if rst_n_io_i = '0' then
ll_addr_o <= (others => '0');
-- ML
muxed <= (others => '0');
-- ML
else
for i in 0 to g_num_ports-1 loop
if(io(i).ll_grant = '1') then
-- ML
--muxed := io(i).ll_addr;
muxed <= io(i).ll_addr;
-- ML
muxed := io(i).ll_addr;
end if;
end loop; -- i
end loop;
ll_addr_o <= muxed;
end if;
end if;
......
modules/wrsw_swcore/swc_multiport_linked_list.vhd
View file @ c153df5b
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-26
-- Last update: 2012-02-16
-- Last update: 2012-03-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -104,9 +104,7 @@ entity swc_multiport_linked_list is
-- requested data
free_pck_data_o : out std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
-------- reading by Multiport Memory (direct access, different clock domain) -------
-- clock of the MPM's core
mpm_rpath_clk_i : in std_logic;
-------- reading by Multiport Memory (direct access) -------
-- requested address, needs to be valid till write_done_o=HIGH
mpm_rpath_addr_i : in std_logic_vector(g_addr_width - 1 downto 0);
-- requested data
......@@ -196,7 +194,8 @@ begin -- syn
PAGE_INDEX_LINKED_LIST_MPM : generic_dpram
generic map (
g_data_width => g_data_width,-- one bit for validating the data
g_size => g_page_num
g_size => g_page_num,
g_dual_clock=> false
)
port map (
-- Port A -- writing
......@@ -208,7 +207,7 @@ begin -- syn
qa_o => open,
-- Port B -- reading
clkb_i => mpm_rpath_clk_i,
clkb_i => clk_i,
bweb_i => (others => '1'),
web_i => '0',
ab_i => mpm_rpath_addr_i,
......@@ -371,4 +370,4 @@ begin -- syn
end generate;
end syn;
\ No newline at end of file
end syn;
modules/wrsw_swcore/swc_swcore_pkg.vhd
View file @ c153df5b
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN BE-Co-HT
-- Created : 2010-04-08
-- Last update: 2012-01-24
-- Last update: 2012-03-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -155,7 +155,6 @@ package swc_swcore_pkg is
free_pck_read_done_o : out std_logic_vector(g_num_ports - 1 downto 0);
free_pck_data_o : out std_logic_vector(g_num_ports * g_data_width - 1 downto 0);
mpm_rpath_clk_i : in std_logic;
mpm_rpath_addr_i : in std_logic_vector(g_addr_width - 1 downto 0);
mpm_rpath_data_o : out std_logic_vector(g_data_width - 1 downto 0)
);
......@@ -175,7 +174,8 @@ package swc_swcore_pkg is
g_mpm_data_width : integer ; -- it needs to be wb_data_width + wb_addr_width
g_page_size : integer ;
g_partial_select_width : integer ;
g_ll_data_width : integer
g_ll_data_width : integer ;
g_port_index : integer
);
port (
clk_i : in std_logic;
......
modules/wrsw_swcore/xswc_core.vhd
View file @ c153df5b
......@@ -6,7 +6,7 @@
-- Author : Maciej Lipinski
-- Company : CERN BE-Co-HT
-- Created : 2010-10-29
-- Last update: 2012-02-02
-- Last update: 2012-03-12
-- Platform : FPGA-generic
-- Standard : VHDL'87
-------------------------------------------------------------------------------
......@@ -285,7 +285,8 @@ architecture rtl of xswc_core is
g_mpm_data_width => c_mpm_data_width,
g_page_size => g_mpm_page_size,
g_partial_select_width => c_mpm_partial_sel_width,
g_ll_data_width => c_ll_data_width
g_ll_data_width => c_ll_data_width,
g_port_index => i
)
port map (
clk_i => clk_i,
......@@ -481,7 +482,6 @@ architecture rtl of xswc_core is
write_addr_i => ib2ll_addr,
write_data_i => ib2ll_data,
mpm_rpath_clk_i => clk_mpm_core_i,
mpm_rpath_addr_i => mpm2ll_addr,
mpm_rpath_data_o => ll2mpm_data,
......
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