Skip to content

W
wr-switch-hdl
Commit b5af21d7 authored by li hongming's avatar li hongming
Browse files
Options

Revert some small modification to make it follow the main branch.

parent fd2ace7e
Hide whitespace changes
Inline Side-by-side
Showing with 91 additions and 102 deletions
Manifest.py
View file @ b5af21d7
......@@ -2,7 +2,6 @@ modules = { "local" : [
"modules/wrsw_nic",
"modules/wrsw_rt_subsystem",
"modules/wrsw_txtsu",
"modules/wrsw_ext_board",
"modules/wrsw_swcore",
"modules/wrsw_rtu",
"modules/wrsw_tru",
......
modules/wrsw_rt_subsystem/wrsw_rt_subsystem.vhd
View file @ b5af21d7
......@@ -59,7 +59,7 @@ entity wrsw_rt_subsystem is
clk_aux_p_o : out std_logic;
clk_aux_n_o : out std_logic;
clk_500_o : out std_logic;
rst_n_i : in std_logic;
rst_n_o : out std_logic;
......@@ -215,6 +215,7 @@ architecture rtl of wrsw_rt_subsystem is
slave_o : out t_wishbone_slave_out);
end component;
-- interconnect layout:
-- 0x00000 - 0x10000: RAM
-- 0x10000 - 0x10100: UART
......@@ -361,9 +362,9 @@ begin -- rtl
clk_fb_i(0) => clk_ref_i,
clk_dmtd_i => clk_dmtd_i,
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
pps_csync_p1_i => pps_csync,
pps_csync_p1_i => pps_csync,
pps_ext_a_i => pps_ext_i,
dac_dmtd_data_o => dac_dmtd_data,
dac_dmtd_load_o => dac_dmtd_load,
......@@ -494,7 +495,7 @@ begin -- rtl
rst_n_o <= gpio_out(3);
ext_pll_reset_n_o <= gpio_out(4);
ext_pll_sync_n_o <= '1';
U_Main_DAC : gc_serial_dac
generic map (
g_num_data_bits => 16,
......
platform/xilinx/ext_pll_100_to_62m.vhd
View file @ b5af21d7
......@@ -79,7 +79,6 @@ port
clk_ext_mul_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_100_to_62m;
......@@ -179,7 +178,7 @@ begin
LOCKED => locked_o,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => powerdown_i,
PWRDWN => '0',
RST => rst_a_i);
-- Output buffering
......
platform/xilinx/ext_pll_10_to_100.vhd
View file @ b5af21d7
......@@ -79,7 +79,6 @@ port
clk_ext_100_o : out std_logic;
-- Status and control signals
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic
);
end ext_pll_10_to_100;
......@@ -179,7 +178,7 @@ begin
LOCKED => locked_o,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => powerdown_i,
PWRDWN => '0',
RST => rst_a_i);
-- Output buffering
......
top/bare_top/scb_top_bare.vhd
View file @ b5af21d7
......@@ -85,8 +85,8 @@ entity scb_top_bare is
-- External 10MHz clock input
clk_ext_i : in std_logic;
-- External 62.5MHz clock input (from 10MHz)
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_ext_mul_i : in std_logic;
clk_ext_mul_locked_i : in std_logic;
clk_aux_p_o : out std_logic; -- going to CLK2 SMC on the front pannel, by
clk_aux_n_o : out std_logic; -- default it's 10MHz, but is configurable
......@@ -116,8 +116,9 @@ entity scb_top_bare is
dac_helper_data_o : out std_logic;
dac_main_sync_n_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
dac_main_sclk_o : out std_logic;
dac_main_data_o : out std_logic;
-------------------------------------------------------------------------------
-- AD9516 PLL Control signals
......@@ -336,6 +337,8 @@ architecture rtl of scb_top_bare is
signal swc_wdog_out : t_swc_fsms_array(c_NUM_PORTS downto 0);
signal ep_stop_traffic : std_logic;
signal ep_links_up : std_logic_vector(c_NUM_PORTS downto 0);
function f_fabric_2_slv (
......@@ -472,6 +475,8 @@ begin
I1 => clk_ref_i, -- both are 62.5 MHz
S => sel_clk_sys_int);
U_Intercon : xwb_sdb_crossbar
generic map (
g_num_masters => 1,
......@@ -520,7 +525,7 @@ begin
clk_sys_i => clk_sys,
clk_dmtd_i => clk_dmtd_i,
clk_rx_i => clk_rx_vec,
clk_ext_i => clk_ext_i, -- FIXME: UGLY HACK
clk_ext_i => clk_ext_i,
clk_ext_mul_i => clk_ext_mul_i,
clk_ext_mul_locked_i => clk_ext_mul_locked_i,
clk_aux_p_o => clk_aux_p_o,
......
top/bare_top/wrsw_components_pkg.vhd
View file @ b5af21d7
......@@ -336,7 +336,7 @@ package wrsw_components_pkg is
rtu2tru_o : out t_rtu2tru;
tru_enabled_i: in std_logic;
-----------------------------------
wb_i : in t_wishbon ext_board_detected_i: in std_logic;e_slave_in;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out);
end component;
......
top/bare_top/wrsw_top_pkg.vhd
View file @ b5af21d7
......@@ -200,6 +200,7 @@ package wrsw_top_pkg is
rmon_events_o : out std_logic_vector(g_port_mask_bits*g_rmon_events_pp-1 downto 0));
end component;
component wrsw_rt_subsystem
generic (
g_num_rx_clocks : integer;
......@@ -334,7 +335,6 @@ package wrsw_top_pkg is
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111");
end component;
component xswc_core is
generic(
g_interface_mode : t_wishbone_interface_mode := PIPELINED;
......
top/scb_18ports/scb_top_synthesis.ucf
View file @ b5af21d7
......@@ -22,13 +22,6 @@ NET "ext_clk_62mhz_n_i" LOC = AN34;
NET "sensors_scl_b" LOC=G13;
NET "sensors_sda_b" LOC=H14;
#NET "dbg_clk_ext_o" LOC=AM33;
#NET "spll_dbg_o<0>" LOC=AL33;
#NET "spll_dbg_o<1>" LOC=AE29;
#NET "spll_dbg_o<2>" LOC=AE28;
#NET "spll_dbg_o<3>" LOC=AM32;
#NET "spll_dbg_o<4>" LOC=AN32;
#NET "spll_dbg_o<5>" LOC=AP33;
#EBI BUS
#NET "cpu_clk_i" LOC="";
......@@ -1434,10 +1427,10 @@ TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_i" TO "U_swcore_pll_clkout0" 20 ns
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_i" 20 ns DATAPATHONLY;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
......
top/scb_18ports/scb_top_synthesis.vhd
View file @ b5af21d7
......@@ -197,10 +197,8 @@ entity scb_top_synthesis is
sensors_sda_b: inout std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic
-- dbg_clk_ext_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)
);
end scb_top_synthesis;
......@@ -210,9 +208,9 @@ architecture Behavioral of scb_top_synthesis is
component swcore_pll is
port
(-- Clock in ports
clk_sys_i : in std_logic;
clk_sys_i : in std_logic;
-- Clock out ports
clk_aux_o : out std_logic
clk_aux_o : out std_logic
);
end component;
......@@ -221,7 +219,6 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_i : in std_logic;
clk_ext_100_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -230,7 +227,6 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_100_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -252,6 +248,8 @@ architecture Behavioral of scb_top_synthesis is
-- Clocks
-------------------------------------------------------------------------------
signal clk_sys_startup : std_logic;
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
......@@ -387,8 +385,8 @@ architecture Behavioral of scb_top_synthesis is
i2c_sda_oen_o : out std_logic_vector(2 downto 0);
i2c_sda_o : out std_logic_vector(2 downto 0);
i2c_sda_i : in std_logic_vector(2 downto 0) := "111";
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
mb_fan1_pwm_o : out std_logic;
mb_fan2_pwm_o : out std_logic;
spll_dbg_o : out std_logic_vector(5 downto 0)
);
end component;
......@@ -415,7 +413,6 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
clk_sys_dbg_o <= clk_sys;
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -508,7 +505,7 @@ clk_sys_dbg_o <= clk_sys;
O => clk_ref,
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
DIFF_TERM => true,
......@@ -518,8 +515,8 @@ clk_sys_dbg_o <= clk_sys;
I => fpga_clk_dmtd_p_i,
IB => fpga_clk_dmtd_n_i);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
U_swcore_pll: swcore_pll port map ( clk_sys_i => clk_ref, clk_aux_o => clk_aux);
U_SYS_PLL : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
......@@ -559,7 +556,7 @@ clk_sys_dbg_o <= clk_sys;
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if g_with_ext_AD9516 = true generate
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
U_Buf_ext_clk_62mhz : IBUFGDS
generic map (
......@@ -582,10 +579,24 @@ clk_sys_dbg_o <= clk_sys;
end generate gen_with_ext_AD9516;
gen_without_ext_AD9516 : if g_with_ext_AD9516 = false generate
local_reset <= not sys_rst_n_i;
gen_without_ext_AD9516 : if (not g_with_ext_AD9516) generate
U_Ext_PLL1: ext_pll_10_to_100
port map(
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
port map(
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
......@@ -594,25 +605,6 @@ clk_sys_dbg_o <= clk_sys;
rst_n_i => sys_rst_n_i,
pulse_i => local_reset,
extended_o => ext_pll_reset);
U_Ext_PLL1: ext_pll_10_to_100
port map(
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
powerdown_i => '1',
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
port map(
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
powerdown_i => '1',
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
end generate gen_without_ext_AD9516;
------------------------------------------------
......@@ -745,6 +737,8 @@ clk_sys_dbg_o <= clk_sys;
led_act_o(i) <= '0';
end generate gen_terminate_unused_phys;
-----------------------------------------------------------------------------
-- "Bare" top module instantiation
-----------------------------------------------------------------------------
......@@ -760,8 +754,7 @@ clk_sys_dbg_o <= clk_sys;
g_with_PSTATS => true,
g_with_muxed_CS => false,
g_with_watchdog => true,
g_inj_per_EP => "00" & x"0000"
)
g_inj_per_EP => "00" & x"0000")
port map (
sys_rst_n_i => sys_rst_n_i,
clk_startup_i => clk_sys_startup,
......@@ -786,6 +779,7 @@ clk_sys_dbg_o <= clk_sys;
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
--pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......@@ -817,7 +811,7 @@ clk_sys_dbg_o <= clk_sys;
i2c_sda_i => i2c_sda_in,
mb_fan1_pwm_o => mb_fan1_pwm_o,
mb_fan2_pwm_o => mb_fan2_pwm_o,
spll_dbg_o => spll_dbg_o);
spll_dbg_o => open);
i2c_scl_in(1 downto 0) <= mbl_scl_b(1 downto 0);
i2c_sda_in(1 downto 0) <= mbl_sda_b(1 downto 0);
......
top/scb_8ports/scb_top_synthesis.ucf
View file @ b5af21d7
......@@ -447,16 +447,16 @@ TIMESPEC ts_ignore_xclk1 = FROM "fpga_clk_ref_i" TO "U_swcore_pll_clkout0" 20 ns
TIMESPEC ts_ignore_xclk2 = FROM "U_swcore_pll_clkout0" TO "fpga_clk_ref_i" 20 ns DATAPATHONLY;
# Avoid noisy DFFs near DMTD demodulation DFF
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT_internal/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d0" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d1" LOC = SLICE_X1Y22;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d0" AREA_GROUP = "pblock_ext_dmtd_2";
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_with_ext_clock_input.U_DMTD_EXT/clk_i_d1" AREA_GROUP = "pblock_ext_dmtd_2";
AREA_GROUP "pblock_ext_dmtd_2" RANGE=SLICE_X0Y19:SLICE_X11Y24;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB18_X0Y8:RAMB18_X0Y9;
AREA_GROUP "pblock_ext_dmtd_2" RANGE=RAMB36_X0Y4:RAMB36_X0Y4;
AREA_GROUP "pblock_ext_dmtd_2" GROUP=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
AREA_GROUP "pblock_ext_dmtd_2" PLACE=CLOSED;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" LOC = SLICE_X101Y148;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d0" LOC = SLICE_X101Y148;
INST "U_Real_Top/U_RT_Subsystem/U_SoftPLL/U_Wrapped_Softpll/gen_feedback_dmtds[0].DMTD_FB/clk_i_d1" AREA_GROUP = "pblock_dmtd_feedback";
......
top/scb_8ports/scb_top_synthesis.vhd
View file @ b5af21d7
......@@ -216,9 +216,9 @@ architecture Behavioral of scb_top_synthesis is
component swcore_pll is
port
(-- Clock in ports
clk_sys_i : in std_logic;
clk_sys_i : in std_logic;
-- Clock out ports
clk_aux_o : out std_logic
clk_aux_o : out std_logic
);
end component;
......@@ -227,7 +227,6 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_i : in std_logic;
clk_ext_100_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -236,7 +235,6 @@ architecture Behavioral of scb_top_synthesis is
clk_ext_100_i : in std_logic;
clk_ext_mul_o : out std_logic;
rst_a_i : in std_logic;
powerdown_i : in std_logic;
locked_o : out std_logic);
end component;
......@@ -262,8 +260,6 @@ architecture Behavioral of scb_top_synthesis is
signal clk_sys, clk_ref, clk_25mhz , clk_dmtd : std_logic;
signal pllout_clk_fb : std_logic;
attribute maxskew: string;
attribute maxskew of clk_dmtd : signal is "1.0ns";
-----------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------
......@@ -298,6 +294,7 @@ architecture Behavioral of scb_top_synthesis is
signal clk_gtx8_11 : std_logic;
signal clk_gtx12_15 : std_logic;
signal clk_gtx16_19 : std_logic;
signal clk_gtx : std_logic_vector(c_NUM_PHYS-1 downto 0);
signal cpu_nwait_int : std_logic;
......@@ -421,7 +418,7 @@ architecture Behavioral of scb_top_synthesis is
signal TRIG3 : std_logic_vector(31 downto 0);
begin
clk_sys_dbg_o <= clk_sys;
clk_sys_dbg_o <= clk_sys;
--chipscope_icon_1 : chipscope_icon
-- port map (
......@@ -515,6 +512,8 @@ clk_sys_dbg_o <= clk_sys;
I => fpga_clk_ref_p_i,
IB => fpga_clk_ref_n_i);
U_Buf_CLK_DMTD : IBUFGDS
generic map (
DIFF_TERM => true,
......@@ -565,7 +564,7 @@ clk_sys_dbg_o <= clk_sys;
I => clk_ext_i,
O => clk_ext);
gen_with_ext_AD9516 : if g_with_ext_AD9516 = true generate
gen_with_ext_AD9516 : if (g_with_ext_AD9516) generate
U_Buf_ext_clk_62mhz : IBUFGDS
generic map (
......@@ -588,11 +587,26 @@ clk_sys_dbg_o <= clk_sys;
end generate gen_with_ext_AD9516;
gen_without_ext_AD9516 : if g_with_ext_AD9516 = false generate
local_reset <= not sys_rst_n_i;
gen_without_ext_AD9516 : if (not g_with_ext_AD9516) generate
U_Ext_PLL1: ext_pll_10_to_100
port map(
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
port map(
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
locked_o => ext_pll_62_locked);
U_Extend_EXT_Reset: gc_extend_pulse
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
local_reset <= not sys_rst_n_i;
U_Extend_EXT_Reset: gc_extend_pulse
generic map (
g_width => 1000)
port map(
......@@ -601,24 +615,6 @@ clk_sys_dbg_o <= clk_sys;
pulse_i => local_reset,
extended_o => ext_pll_reset);
U_Ext_PLL1: ext_pll_10_to_100
port map(
clk_ext_i => clk_ext,
clk_ext_100_o => clk_ext_100,
rst_a_i => ext_pll_reset,
powerdown_i => '1',
locked_o => ext_pll_100_locked);
U_Ext_PLL2: ext_pll_100_to_62m
port map(
clk_ext_100_i => clk_ext_100,
clk_ext_mul_o => clk_ext_mul,
rst_a_i => ext_pll_reset,
powerdown_i => '1',
locked_o => ext_pll_62_locked);
clk_ext_mul_locked <= ext_pll_100_locked and ext_pll_62_locked;
end generate gen_without_ext_AD9516;
------------------------------------------------
......@@ -751,6 +747,8 @@ clk_sys_dbg_o <= clk_sys;
led_act_o(i) <= '0';
end generate gen_terminate_unused_phys;
-----------------------------------------------------------------------------
-- "Bare" top module instantiation
-----------------------------------------------------------------------------
......@@ -792,6 +790,7 @@ clk_sys_dbg_o <= clk_sys;
dac_main_sync_n_o => dac_main_sync_n_o,
dac_main_sclk_o => dac_main_sclk_o,
dac_main_data_o => dac_main_data_o,
-- pll_status_i => clk_ext,
pll_mosi_o => pll_mosi_o,
pll_miso_i => pll_miso_i,
pll_sck_o => pll_sck_o,
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment