testbench: added system-level testbench

d4518677 · Tomasz Wlostowski · d3616a93 · d4518677 · d4518677 · d4518677
Commit d4518677 authored Mar 14, 2012 by Tomasz Wlostowski
Showing with 106 additions and 0 deletions

Manifest.py testbench/top_level/Manifest.py +8 -0

main.sv testbench/top_level/main.sv +60 -0

run.do testbench/top_level/run.do +10 -0

wave.do testbench/top_level/wave.do +28 -0

No files found.
--- a/testbench/top_level/Manifest.py
+++ b/testbench/top_level/Manifest.py
+action = "simulation"
+fetchto = "../../ip_cores"
+vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
+
+files = [ "main.sv" ]
+
+modules = { "local" :  [ "../..", "../../top/spec", "gn4124_bfm"] }
+
--- a/testbench/top_level/main.sv
+++ b/testbench/top_level/main.sv
+`timescale 1ns/1ps
+
+`include "gn4124_bfm.svh"   
+
+const uint64_t BASE_WRPC = 'h0080000;
+const uint64_t BASE_NIC = 'ha0000;
+const uint64_t BASE_VIC = 'hc0000;
+const uint64_t BASE_TXTSU = 'h000d0000;
+const uint64_t BASE_DIO = 'h000e0000;
+
+module main;
+   reg clk_125m_pllref = 0;
+   reg clk_20m_vcxo = 0;
+   
+   always #4ns clk_125m_pllref <= ~clk_125m_pllref;
+   always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
+   
+   IGN4124PCIMaster I_Gennum ();
+
+   wr_nic_top
+     DUT (
+          .clk_125m_pllref_p_i(clk_125m_pllref),
+          .clk_125m_pllref_n_i(~clk_125m_pllref),
+          .clk_20m_vcxo_i(clk_20m_vcxo),
+
+          `GENNUM_WIRE_SPEC_PINS(I_Gennum)
+	  );
+
+   initial begin
+      uint64_t rval;
+      
+      CBusAccessor acc ;
+      acc = I_Gennum.get_accessor();
+      @(posedge I_Gennum.ready);
+      
+      acc.write(BASE_WRPC + 'h100, 'hdeadbeef);
+      acc.write(BASE_WRPC + 'h104, 'hcafebabe);
+
+      acc.read(BASE_WRPC + 'h100, rval);
+      $display("MemReadback1 %x", rval);
+      acc.read(BASE_WRPC + 'h104, rval);
+      $display("MemReadback2 %x", rval);
+
+      acc.write(BASE_VIC + 'h4, 'h1); // enable IRQ 0
+      acc.write(BASE_VIC + 'h0, 'h3); // positive polarity, enable VIC
+
+      acc.write(BASE_VIC + 'h18, 'h1); // software IRQ trigger
+
+      
+      
+      
+      
+      
+   end
+   
+   
+endmodule // main
+
+
+
--- a/testbench/top_level/run.do
+++ b/testbench/top_level/run.do
+vlog -sv main.sv +incdir+"." +incdir+gn4124_bfm +incdir+../../sim
+make -f Makefile
+vsim -L unisim work.main -voptargs="+acc"
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+do wave.do
+radix -hexadecimal
+run 25us
+wave zoomfull
+radix -hexadecimal
--- a/testbench/top_level/wave.do
+++ b/testbench/top_level/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/U_VIC/g_interface_mode
+add wave -noupdate /main/DUT/U_VIC/g_address_granularity
+add wave -noupdate /main/DUT/U_VIC/g_num_interrupts
+add wave -noupdate /main/DUT/U_VIC/clk_sys_i
+add wave -noupdate /main/DUT/U_VIC/rst_n_i
+add wave -noupdate /main/DUT/U_VIC/slave_i
+add wave -noupdate /main/DUT/U_VIC/slave_o
+add wave -noupdate /main/DUT/U_VIC/irqs_i
+add wave -noupdate /main/DUT/U_VIC/irq_master_o
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {2367015 ps} 0}
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 1
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ps} {26250 ns}