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Commit a3a52692 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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testbench/top_level: trivial top-level testbench

parent 9a6cbb5e
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testbench/top_level/Manifest.py
View file @ a3a52692
action = "simulation"
target = "xilinx"
fetchto = "../../ip_cores"
vlog_opt="+incdir+../../sim +incdir+gn4124_bfm"
files = [ "main.sv", "../../ip_cores/wr-cores/platform/xilinx/wr_xilinx_pkg.vhd" ]
files = [ "main.sv" ]
modules = { "local" : [ "../..", "../../top/spec", "./gn4124_bfm"] }
testbench/top_level/endpoint_phy_wrapper.svh 0 → 100644
View file @ a3a52692
module endpoint_phy_wrapper
(
input clk_sys_i,
input clk_ref_i,
input clk_rx_i,
input rst_n_i,
IWishboneMaster.master src,
IWishboneSlave.slave snk,
IWishboneMaster.master sys,
output [9:0] td_o,
input [9:0] rd_i,
output txn_o,
output txp_o,
input rxn_i,
input rxp_i
);
wire rx_clock;
parameter g_phy_type = "GTP";
wire[15:0] gtx_data;
wire [1:0]gtx_k;
wire gtx_disparity;
wire gtx_enc_error;
wire [15:0] grx_data;
wire grx_clk;
wire [1:0]grx_k;
wire grx_enc_error;
wire [3:0] grx_bitslide;
wire gtp_rst;
wire tx_clock;
generate
if(g_phy_type == "TBI") begin
assign rx_clock = clk_ref_i;
assign tx_clock = clk_rx_i;
wr_tbi_phy U_Phy
(
.serdes_rst_i (gtp_rst),
.serdes_loopen_i(1'b0),
.serdes_prbsen_i(1'b0),
.serdes_enable_i(1'b1),
.serdes_syncen_i(1'b1),
.serdes_tx_data_i (gtx_data[7:0]),
.serdes_tx_k_i (gtx_k[0]),
.serdes_tx_disparity_o (gtx_disparity),
.serdes_tx_enc_err_o (gtx_enc_error),
.serdes_rx_data_o (grx_data[7:0]),
.serdes_rx_k_o (grx_k[0]),
.serdes_rx_enc_err_o (grx_enc_error),
.serdes_rx_bitslide_o (grx_bitslide),
.tbi_refclk_i (clk_ref_i),
.tbi_rbclk_i (clk_rx_i),
.tbi_td_o (td_o),
.tbi_rd_i (rd_i),
.tbi_syncen_o (),
.tbi_loopen_o (),
.tbi_prbsen_o (),
.tbi_enable_o ()
);
end else if (g_phy_type == "GTX") begin // if (g_phy_type == "TBI")
wr_gtx_phy_virtex6
#(
.g_simulation(1)
) U_PHY
(
.clk_ref_i(clk_ref_i),
.tx_clk_o (tx_clock),
.tx_data_i (gtx_data),
.tx_k_i (gtx_k),
.tx_disparity_o (gtx_disparity),
.tx_enc_err_o(gtx_enc_error),
.rx_rbclk_o (rx_clock),
.rx_data_o (grx_data),
.rx_k_o (grx_k),
.rx_enc_err_o (grx_enc_error),
.rx_bitslide_o (),
.rst_i (!rst_n_i),
.loopen_i (1'b0),
.pad_txn_o (txn_o),
.pad_txp_o (txp_o),
.pad_rxn_i (rxn_i),
.pad_rxp_i (rxp_i)
);
end else if (g_phy_type == "GTP") begin // if (g_phy_type == "TBI")
assign #1 tx_clock = clk_ref_i;
wr_gtp_phy_spartan6
#(
.g_simulation(1)
) U_PHY
(
.gtp_clk_i(clk_ref_i),
.ch0_ref_clk_i(clk_ref_i),
.ch0_tx_data_i (gtx_data[7:0]),
.ch0_tx_k_i (gtx_k[0]),
.ch0_tx_disparity_o (gtx_disparity),
.ch0_tx_enc_err_o(gtx_enc_error),
.ch0_rx_rbclk_o (rx_clock),
.ch0_rx_data_o (grx_data[7:0]),
.ch0_rx_k_o (grx_k[0]),
.ch0_rx_enc_err_o (grx_enc_error),
.ch0_rx_bitslide_o (),
.ch0_rst_i (!rst_n_i),
.ch0_loopen_i (1'b0),
.pad_txn0_o (txn_o),
.pad_txp0_o (txp_o),
.pad_rxn0_i (rxn_i),
.pad_rxp0_i (rxp_i)
);
end // else: !if(g_phy_type == "TBI")
endgenerate
wr_endpoint
#(
.g_simulation (1),
.g_pcs_16bit(g_phy_type == "GTX" ? 1: 0),
.g_rx_buffer_size (1024),
.g_with_rx_buffer(0),
.g_with_timestamper (1),
.g_with_dmtd (0),
.g_with_dpi_classifier (1),
.g_with_vlans (0),
.g_with_rtu (0)
) DUT (
.clk_ref_i (clk_ref_i),
.clk_sys_i (clk_sys_i),
.clk_dmtd_i (clk_ref_i),
.rst_n_i (rst_n_i),
.pps_csync_p1_i (1'b0),
.phy_rst_o (),
.phy_loopen_o (),
.phy_enable_o (),
.phy_syncen_o (),
.phy_ref_clk_i (tx_clock),
.phy_tx_data_o (gtx_data),
.phy_tx_k_o (gtx_k),
.phy_tx_disparity_i (gtx_disparity),
.phy_tx_enc_err_i (gtx_enc_error),
.phy_rx_data_i (grx_data),
.phy_rx_clk_i (rx_clock),
.phy_rx_k_i (grx_k),
.phy_rx_enc_err_i (grx_enc_error),
.phy_rx_bitslide_i (5'b0),
.src_dat_o (snk.dat_i),
.src_adr_o (snk.adr),
.src_sel_o (snk.sel),
.src_cyc_o (snk.cyc),
.src_stb_o (snk.stb),
.src_we_o (snk.we),
.src_stall_i (snk.stall),
.src_ack_i (snk.ack),
.src_err_i(1'b0),
.snk_dat_i (src.dat_o[15:0]),
.snk_adr_i (src.adr[1:0]),
.snk_sel_i (src.sel[1:0]),
.snk_cyc_i (src.cyc),
.snk_stb_i (src.stb),
.snk_we_i (src.we),
.snk_stall_o (src.stall),
.snk_ack_o (src.ack),
.snk_err_o (src.err),
.snk_rty_o (src.rty),
.txtsu_ack_i (1'b1),
.rtu_full_i (1'b0),
.rtu_almost_full_i (1'b0),
.rtu_rq_strobe_p1_o (),
.rtu_rq_smac_o (),
.rtu_rq_dmac_o (),
.rtu_rq_vid_o (),
.rtu_rq_has_vid_o (),
.rtu_rq_prio_o (),
.rtu_rq_has_prio_o (),
.wb_cyc_i(sys.cyc),
.wb_stb_i (sys.stb),
.wb_we_i (sys.we),
.wb_sel_i(sys.sel),
.wb_adr_i(sys.adr[7:0]),
.wb_dat_i(sys.dat_o),
.wb_dat_o(sys.dat_i),
.wb_ack_o (sys.ack)
);
endmodule // endpoint_phy_wrapper
testbench/top_level/gn4124_bfm/gn4124_bfm.svh
View file @ a3a52692
......@@ -163,6 +163,8 @@ GN412X_BFM
task automatic readback(ref uint64_t value);
@(posedge cmd_rddata_valid);
$display("Rdbk: %x", cmd_rddata);
value = cmd_rddata;
@(negedge cmd_rddata_valid);
endtask // readback
......@@ -185,6 +187,8 @@ class CBusAccessor_Gennum extends CBusAccessor;
for(i=0;i<addr.size();i++)
begin
$display("GN-write %x %x\n", addr[i], data[i]);
$sformat(cmd,"wr FF000000%08X F %08X", addr[i], data[i]);
send_cmd(cmd);
end
......@@ -195,6 +199,8 @@ class CBusAccessor_Gennum extends CBusAccessor;
int i;
uint64_t tmp;
$display("rd %x\n", addr[0]);
if(size != 4)
......@@ -203,10 +209,10 @@ class CBusAccessor_Gennum extends CBusAccessor;
for(i=0;i<addr.size();i++)
begin
$sformat(cmd,"rd FF000000%08X F", addr[i]);
fork
// fork
send_cmd(cmd);
readback(tmp);
join
// join
data[i] = tmp;
......
testbench/top_level/main.sv
View file @ a3a52692
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
`include "gn4124_bfm.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "drivers/simdrv_wrsw_nic.svh"
`include "endpoint_regs.v"
`include "endpoint_mdio.v"
`include "regs/dio_regs.vh"
`include "regs/vic_regs.vh"
`include "endpoint_phy_wrapper.svh"
const uint64_t BASE_WRPC = 'h0080000;
const uint64_t BASE_NIC = 'h00c0000;
const uint64_t BASE_VIC = 'h00e0000;
const uint64_t BASE_TXTSU ='h00e1000;
const uint64_t BASE_DIO = 'h00e2000;
const uint64_t BASE_DIO = 'h00e2300;
module main;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
reg clk_sys = 0;
reg rst_n = 0;
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
always #8ns clk_sys <= ~clk_sys;
always #20ns clk_20m_vcxo <= ~clk_20m_vcxo;
initial #200ns rst_n = 1;
IWishboneMaster
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_source
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneSlave
#(
.g_data_width(16),
.g_addr_width(2))
U_wrf_sink
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
IWishboneMaster
#(
.g_data_width(32),
.g_addr_width(7))
U_sys_bus_master
(
.clk_i(clk_sys),
.rst_n_i(rst_n)
);
/* -----\/----- EXCLUDED -----\/-----
endpoint_phy_wrapper
#(
.g_phy_type("GTP"))
U_Wrapped_EP_GTP
(
.clk_sys_i(clk_sys),
.clk_ref_i(clk_125m_pllref),
.clk_rx_i(clk_125m_pllref),
.rst_n_i(rst_n),
.snk (U_wrf_sink.slave),
.src(U_wrf_source.master),
.sys(U_sys_bus_master.master),
.txn_o(rxn),
.txp_o(rxp),
.rxn_i(txn),
.rxp_i(txp)
);
-----/\----- EXCLUDED -----/\----- */
IGN4124PCIMaster I_Gennum ();
reg [4:0] dio_in = 0;
wr_nic_sdb_top
DUT (
.clk_125m_pllref_p_i(clk_125m_pllref),
.clk_125m_pllref_n_i(~clk_125m_pllref),
.clk_125m_pllref_n_i(~clk_125m_pllref),
. fpga_pll_ref_clk_101_p_i(clk_125m_pllref),
. fpga_pll_ref_clk_101_n_i(~clk_125m_pllref),
.clk_20m_vcxo_i(clk_20m_vcxo),
`GENNUM_WIRE_SPEC_PINS(I_Gennum)
`GENNUM_WIRE_SPEC_PINS(I_Gennum),
.sfp_txp_o(txp),
.sfp_txn_o(txn),
.sfp_rxp_i(rxp),
.sfp_rxn_i(rxn),
.dio_n_i(~dio_in),
.dio_p_i(dio_in)
);
task automatic tx_test(int n_tries, int is_q, int unvid, EthPacketSource src, EthPacketSink sink);
EthPacketGenerator gen = new;
EthPacket pkt, tmpl, pkt2;
EthPacket arr[];
int i;
arr = new[n_tries](arr);
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
tmpl.has_smac = 1;
tmpl.is_q = is_q;
tmpl.vid = 100;
tmpl.ethertype = 'h88f7;
//
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(64,64);
for(i=0;i<n_tries;i++)
begin
pkt = gen.gen();
// $display("Tx %d", i);
// pkt.dump();
src.send(pkt);
// $display("Send: %d [dsize %d]", i+1,pkt.payload.size() + 14);
arr[i] = pkt;
end
for(i=0;i<n_tries;i++)
begin
sink.recv(pkt2);
// $display("rx %d", i);
if(unvid)
arr[i].is_q = 0;
if(!arr[i].equal(pkt2))
begin
$display("Fault at %d", i);
arr[i].dump();
pkt2.dump();
$stop;
end
end // for (i=0;i<n_tries;i++)
endtask // tx_test
task send_random(WBPacketSource src);
EthPacketGenerator gen = new;
EthPacket pkt, tmpl;
tmpl = new;
tmpl.src = '{1,2,3,4,5,6};
tmpl.dst = '{'h00, 'h50, 'hca, 'hfe, 'hba, 'hbe};
tmpl.has_smac = 1;
tmpl.vid = 100;
tmpl.ethertype = 'h88f7;
gen.set_randomization(EthPacketGenerator::SEQ_PAYLOAD /* | EthPacketGenerator::TX_OOB*/) ;
gen.set_template(tmpl);
gen.set_size(64,64);
pkt = gen.gen();
src.send(pkt);
endtask // send_random
initial begin
uint64_t rval;
/*
uint64_t rval;
int i;
NICPacketSource nic_src;
NICPacketSink nic_snk;
CSimDrv_NIC drv;
CBusAccessor acc ;
acc = I_Gennum.get_accessor();
@(posedge I_Gennum.ready);
drv = new (acc, BASE_NIC);
drv.init();
nic_src = new (drv);
nic_snk = new (drv);
*/
CWishboneAccessor sys_bus;
WBPacketSource src = new(U_wrf_source.get_accessor());
WBPacketSink sink = new(U_wrf_sink.get_accessor());
// CSimDrv_WR_Endpoint ep_drv;
EthPacket pkt;
CBusAccessor acc ;
int i;
$display("Startup");
acc = I_Gennum.get_accessor();
$display("GnPreReady\n");
@(posedge I_Gennum.ready);
$display("GnReady\n");
acc.write('ha0400, 'h1deadbee); // reset lm32, h20004
acc.write('ha0400, 'h0deadbee);
acc.write(BASE_NIC + `ADDR_NIC_CR, `NIC_CR_RX_EN | `NIC_CR_TX_EN);
acc.write(BASE_NIC + `ADDR_NIC_EIC_IER, 'h7);
acc.write(BASE_NIC + `BASE_NIC_DRX + 8, (1000) << 16);
acc.write(BASE_NIC + `BASE_NIC_DRX + 0, 1);
acc.write('hc0000, 'h0deadbee);
acc.write('he0000, 'h0deadbee);
acc.write('he1000, 'h0deadbee);
acc.write('he2000, 'h0deadbee);
acc.write(BASE_VIC + `ADDR_VIC_CTL, `VIC_CTL_ENABLE | `VIC_CTL_EMU_EDGE | (100<<3));
acc.write(BASE_VIC + `ADDR_VIC_IER, 'hff);
acc.write(BASE_VIC + `ADDR_VIC_SWIR, 'h1);
#1us;
acc.write(BASE_VIC + `ADDR_VIC_EOIR, 'h1);
acc.write(BASE_WRPC + 'h100, 'hdeadbeef);
acc.write(BASE_WRPC + 'h104, 'hcafebabe);
$display("AccWriteDone");
#1us;
$stop;
acc.read(BASE_WRPC + 'h100, rval);
$display("MemReadback1 %x", rval);
acc.read(BASE_WRPC + 'h104, rval);
//$display("MemReadback2 %x", rval);
#150us;
/* -----\/----- EXCLUDED -----\/-----
acc.write(BASE_VIC + 'h4, 'h1); // enable IRQ 0
acc.write(BASE_VIC + 'h0, 'h3); // positive polarity, enable VIC
acc.write(BASE_VIC + 'h18, 'h1); // software IRQ trigger
-----/\----- EXCLUDED -----/\----- */
$display("ConfigDIO");
acc.write(BASE_DIO + `ADDR_DIO_TRIG0, 0);
acc.write(BASE_DIO + `ADDR_DIO_TRIGH0, 0);
acc.write(BASE_DIO + `ADDR_DIO_CYC0, 'h3000);
acc.write(BASE_DIO + `ADDR_DIO_OUT, 'h01);
acc.write(BASE_DIO + `ADDR_DIO_PROG0_PULSE, 'h10);
acc.write(BASE_DIO + `ADDR_DIO_LATCH, 'h1);
acc.write(BASE_DIO + `ADDR_DIO_EIC_IER, 'hff);
#100us;
dio_in[0] = 1'b1;
#100ns;
dio_in[0] = 1'b0;
// @(posedge rst_n);
@(posedge clk_sys);
$display("EPInit!\n");
sys_bus = U_sys_bus_master.get_accessor();
sys_bus.set_mode(CLASSIC);
sys_bus.write(`ADDR_EP_ECR, `EP_ECR_TX_EN | `EP_ECR_RX_EN);
sys_bus.write(`ADDR_EP_RFCR, 1518 << `EP_RFCR_MRU_OFFSET);
sys_bus.write(`ADDR_EP_VCR0, 3 << `EP_VCR0_QMODE_OFFSET);
sys_bus.write(`ADDR_EP_TSCR, `EP_TSCR_EN_RXTS);
#700us;
forever begin
send_random(src);
#1us;
end
end
endmodule // main
testbench/top_level/run.do
View file @ a3a52692
vlog -sv main.sv +incdir+"." +incdir+gn4124_bfm +incdir+../../sim
make -f Makefile
vsim -L unisim work.main -voptargs="+acc"
#make -f Makefile
vsim -t 10fs -L secureip -L unisim work.main -voptargs="+acc"
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
......
testbench/top_level/wave.do
View file @ a3a52692
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/DUT/g_nic_usedma
add wave -noupdate /main/DUT/clk_20m_vcxo_i
add wave -noupdate /main/DUT/clk_125m_pllref_p_i
add wave -noupdate /main/DUT/clk_125m_pllref_n_i
add wave -noupdate /main/DUT/L_CLKp
add wave -noupdate /main/DUT/L_CLKn
add wave -noupdate /main/DUT/L_RST_N
add wave -noupdate /main/DUT/GPIO
add wave -noupdate /main/DUT/P2L_RDY
add wave -noupdate /main/DUT/P2L_CLKn
add wave -noupdate /main/DUT/P2L_CLKp
add wave -noupdate /main/DUT/P2L_DATA
add wave -noupdate /main/DUT/P2L_DFRAME
add wave -noupdate /main/DUT/P2L_VALID
add wave -noupdate /main/DUT/P_WR_REQ
add wave -noupdate /main/DUT/P_WR_RDY
add wave -noupdate /main/DUT/RX_ERROR
add wave -noupdate /main/DUT/L2P_DATA
add wave -noupdate /main/DUT/L2P_DFRAME
add wave -noupdate /main/DUT/L2P_VALID
add wave -noupdate /main/DUT/L2P_CLKn
add wave -noupdate /main/DUT/L2P_CLKp
add wave -noupdate /main/DUT/L2P_EDB
add wave -noupdate /main/DUT/L2P_RDY
add wave -noupdate /main/DUT/L_WR_RDY
add wave -noupdate /main/DUT/P_RD_D_RDY
add wave -noupdate /main/DUT/TX_ERROR
add wave -noupdate /main/DUT/VC_RDY
add wave -noupdate /main/DUT/LED_RED
add wave -noupdate /main/DUT/LED_GREEN
add wave -noupdate /main/DUT/dac_sclk_o
add wave -noupdate /main/DUT/dac_din_o
add wave -noupdate /main/DUT/dac_clr_n_o
add wave -noupdate /main/DUT/dac_cs1_n_o
add wave -noupdate /main/DUT/dac_cs2_n_o
add wave -noupdate /main/DUT/fpga_scl_b
add wave -noupdate /main/DUT/fpga_sda_b
add wave -noupdate /main/DUT/button1_i
add wave -noupdate /main/DUT/button2_i
add wave -noupdate /main/DUT/thermo_id
add wave -noupdate /main/DUT/sfp_txp_o
add wave -noupdate /main/DUT/sfp_txn_o
add wave -noupdate /main/DUT/sfp_rxp_i
add wave -noupdate /main/DUT/sfp_rxn_i
add wave -noupdate /main/DUT/sfp_mod_def0_b
add wave -noupdate /main/DUT/sfp_mod_def1_b
add wave -noupdate /main/DUT/sfp_mod_def2_b
add wave -noupdate /main/DUT/sfp_rate_select_b
add wave -noupdate /main/DUT/sfp_tx_fault_i
add wave -noupdate /main/DUT/sfp_tx_disable_o
add wave -noupdate /main/DUT/sfp_los_i
add wave -noupdate /main/DUT/dio_clk_p_i
add wave -noupdate /main/DUT/dio_clk_n_i
add wave -noupdate /main/DUT/dio_n_i
add wave -noupdate /main/DUT/dio_p_i
add wave -noupdate /main/DUT/dio_n_o
add wave -noupdate /main/DUT/dio_p_o
add wave -noupdate /main/DUT/dio_oe_n_o
add wave -noupdate /main/DUT/dio_term_en_o
add wave -noupdate /main/DUT/dio_onewire_b
add wave -noupdate /main/DUT/dio_sdn_n_o
add wave -noupdate /main/DUT/dio_sdn_ck_n_o
add wave -noupdate /main/DUT/dio_led_top_o
add wave -noupdate /main/DUT/dio_led_bot_o
add wave -noupdate /main/DUT/fmc_scl_b
add wave -noupdate /main/DUT/fmc_sda_b
add wave -noupdate /main/DUT/uart_rxd_i
add wave -noupdate /main/DUT/uart_txd_o
add wave -noupdate /main/DUT/CONTROL
add wave -noupdate /main/DUT/CLK
add wave -noupdate /main/DUT/TRIG0
add wave -noupdate /main/DUT/TRIG1
add wave -noupdate /main/DUT/TRIG2
add wave -noupdate /main/DUT/TRIG3
add wave -noupdate /main/DUT/l_clk
add wave -noupdate /main/DUT/p2l_pll_locked
add wave -noupdate /main/DUT/rst
add wave -noupdate /main/DUT/dma_adr
add wave -noupdate /main/DUT/dma_dat_i
add wave -noupdate /main/DUT/dma_dat_o
add wave -noupdate /main/DUT/dma_sel
add wave -noupdate /main/DUT/dma_cyc
add wave -noupdate /main/DUT/dma_stb
add wave -noupdate /main/DUT/dma_we
add wave -noupdate /main/DUT/dma_ack
add wave -noupdate /main/DUT/dma_stall
add wave -noupdate /main/DUT/ram_we
add wave -noupdate /main/DUT/ddr_dma_adr
add wave -noupdate /main/DUT/irq_to_gn4124
add wave -noupdate /main/DUT/spi_slave_select
add wave -noupdate /main/DUT/pllout_clk_sys
add wave -noupdate /main/DUT/pllout_clk_dmtd
add wave -noupdate /main/DUT/pllout_clk_fb_pllref
add wave -noupdate /main/DUT/pllout_clk_fb_dmtd
add wave -noupdate /main/DUT/clk_20m_vcxo_buf
add wave -noupdate /main/DUT/clk_125m_pllref
add wave -noupdate /main/DUT/clk_sys
add wave -noupdate /main/DUT/clk_dmtd
add wave -noupdate /main/DUT/dac_rst_n
add wave -noupdate /main/DUT/led_divider
add wave -noupdate /main/DUT/wrc_scl_o
add wave -noupdate /main/DUT/wrc_scl_i
add wave -noupdate /main/DUT/wrc_sda_o
add wave -noupdate /main/DUT/wrc_sda_i
add wave -noupdate /main/DUT/sfp_scl_o
add wave -noupdate /main/DUT/sfp_scl_i
add wave -noupdate /main/DUT/sfp_sda_o
add wave -noupdate /main/DUT/sfp_sda_i
add wave -noupdate /main/DUT/dio
add wave -noupdate /main/DUT/dac_hpll_load_p1
add wave -noupdate /main/DUT/dac_dpll_load_p1
add wave -noupdate /main/DUT/dac_hpll_data
add wave -noupdate /main/DUT/dac_dpll_data
add wave -noupdate /main/DUT/pps
add wave -noupdate /main/DUT/phy_tx_data
add wave -noupdate /main/DUT/phy_tx_k
add wave -noupdate /main/DUT/phy_tx_disparity
add wave -noupdate /main/DUT/phy_tx_enc_err
add wave -noupdate /main/DUT/phy_rx_data
add wave -noupdate /main/DUT/phy_rx_rbclk
add wave -noupdate /main/DUT/phy_rx_k
add wave -noupdate /main/DUT/phy_rx_enc_err
add wave -noupdate /main/DUT/phy_rx_bitslide
add wave -noupdate /main/DUT/phy_rst
add wave -noupdate /main/DUT/phy_loopen
add wave -noupdate /main/DUT/dio_in
add wave -noupdate /main/DUT/dio_out
add wave -noupdate /main/DUT/dio_clk
add wave -noupdate /main/DUT/local_reset_n
add wave -noupdate /main/DUT/button1_synced
add wave -noupdate /main/DUT/wrc_slave_i
add wave -noupdate /main/DUT/wrc_slave_o
add wave -noupdate /main/DUT/owr_en
add wave -noupdate /main/DUT/owr_i
add wave -noupdate /main/DUT/wrpc_ts_o
add wave -noupdate /main/DUT/wrpc_ts_ack_i
add wave -noupdate /main/DUT/tm_time_valid
add wave -noupdate /main/DUT/tm_utc
add wave -noupdate /main/DUT/tm_cycles
add wave -noupdate /main/DUT/wb_irq_data_fifo_dio
add wave -noupdate /main/DUT/nic_src_out
add wave -noupdate /main/DUT/nic_src_in
add wave -noupdate /main/DUT/nic_snk_out
add wave -noupdate /main/DUT/nic_snk_in
add wave -noupdate /main/DUT/nic_dma_in
add wave -noupdate /main/DUT/nic_dma_out
add wave -noupdate /main/DUT/cbar_slave_i
add wave -noupdate /main/DUT/cbar_slave_o
add wave -noupdate /main/DUT/cbar_master_i
add wave -noupdate /main/DUT/cbar_master_o
add wave -noupdate /main/DUT/vic_irq
add wave -noupdate /main/DUT/vic_slave_irq
add wave -noupdate /main/DUT/cbar_slave_adr_words
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/g_interface_mode
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/g_address_granularity
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/g_num_interrupts
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/clk_sys_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/rst_n_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_adr_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_dat_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_dat_o
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_cyc_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_sel_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_stb_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_we_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_ack_o
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_stall_o
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/irqs_i
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/irq_master_o
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/irqs_i_reg
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ctl_enable
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ctl_pol
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ctl_emu_edge
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ctl_emu_len
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_risr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ier
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ier_wr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_idr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_idr_wr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_imr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_var
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_eoir
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_eoir_wr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ivt_ram_addr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ivt_ram_data
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_ivt_ram_rd
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_swir
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/vic_swir_wr
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/got_irq
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/swi_mask
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/current_irq
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/irq_id_encoded
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/state
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_in
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/wb_out
add wave -noupdate /main/DUT/U_VIC/U_Wrapped_VIC/timeout_count
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {250000 ps} 0}
WaveRestoreCursors {{Cursor 1} {19332000000 fs} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
......@@ -169,4 +59,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {6562500 ps}
WaveRestoreZoom {18085113600 fs} {19397625600 fs}
testbench/top_level/wrc.ram 0 → 100644
View file @ a3a52692
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