added clock constraints and undefined pins

7fc1d74f · Peter Jansweijer · 14e625c2 · 7fc1d74f
Commit 7fc1d74f authored Sep 12, 2017 by Peter Jansweijer
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Showing with 16 additions and 15 deletions

clb_abs_calibration.xdc hdl/clb_abs_calibration/vivado/clb_abs_calibration.xdc +16 -15

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--- a/hdl/clb_abs_calibration/vivado/clb_abs_calibration.xdc
+++ b/hdl/clb_abs_calibration/vivado/clb_abs_calibration.xdc
@@ -2,6 +2,7 @@
 #CLOCK & RESET
 set_property PACKAGE_PIN F22 [get_ports clk_20m_vcxo_i]
 set_property IOSTANDARD LVCMOS33 [get_ports clk_20m_vcxo_i]
+create_clock -period 50.000 -name clk_20m_vcxo_i -waveform {0.000 25.000} [get_ports clk_20m_vcxo_i]

 #Bank 16 VCCO - 3.3 V
 set_property PACKAGE_PIN E11 [get_ports RESET]
@@ -122,17 +123,7 @@ set_property PACKAGE_PIN A19 [get_ports LED_LINK]
 set_property IOSTANDARD LVCMOS25 [get_ports LED_LINK]

 ########## To be assigned ###########
-set_property SEVERITY {Warning} [get_drc_checks NSTD-1]
-#CPU_Gnt
-#set_property PACKAGE_PIN ### [get_ports CPU_Gnt]
-#set_property IOSTANDARD LVCMOS25 [get_ports CPU_Gnt]
-#CPU_Req
-#set_property PACKAGE_PIN ### [get_ports CPU_Req]
-#set_property IOSTANDARD LVCMOS25 [get_ports CPU_Req]
-#LED_ACT
-#set_property PACKAGE_PIN ### [get_ports LED_ACT]
-#set_property IOSTANDARD LVCMOS25 [get_ports LED_ACT]
-
+#set_property SEVERITY {Warning} [get_drc_checks NSTD-1]

 #Bank 15 VCCO - 2.5 V
 #set_property PACKAGE_PIN J15 [get_ports DIP_SWITCH[1]]
@@ -352,10 +343,10 @@ set_property IOSTANDARD LVCMOS33 [get_ports SFP_SCL]
 #Bank 116
 set_property PACKAGE_PIN D6 [get_ports FPGA_PLL_REF_CLK0_P]
 #set_property IOSTANDARD LVDS_25 [get_ports FPGA_PLL_REF_CLK0_P]
-
-#Bank 116
+create_clock -period 8.000 -name FPGA_PLL_REF_CLK0_P -waveform {0.000 4.000} [get_ports FPGA_PLL_REF_CLK0_P]
 set_property PACKAGE_PIN D5 [get_ports FPGA_PLL_REF_CLK0_N]
 #set_property IOSTANDARD LVDS_25 [get_ports FPGA_PLL_REF_CLK0_N]
+create_clock -period 8.000 -name FPGA_PLL_REF_CLK0_n -waveform {0.000 4.000} [get_ports FPGA_PLL_REF_CLK0_N]

 #>>>#NET "FPGA_PLL_REF_CLK0_P" TNM_NET = FPGA_PLL_REF_CLK0_P;
 #>>>#TIMESPEC TS_FPGA_PLL_REF_CLK0_P = PERIOD "FPGA_PLL_REF_CLK0_P" 8 ns HIGH 50%;
@@ -642,17 +633,27 @@ set_property IOSTANDARD LVCMOS25 [get_ports dio_led_bot_o]
 #NET "FMC_LA06_N" LOC = AF25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 27
 #NET "Tdc_full" LOC = AF25 | IOSTANDARD = LVCMOS25;    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 27
 #NET "FMC_LA07_P" LOC = U19 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 29
-#NET "CPU_Gnt" LOC = U19 | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 29
 #NET "FMC_LA07_N" LOC = U20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 31
-#NET "CPU_Req" LOC = U20 | IOSTANDARD = LVCMOS25;    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 31
 #NET "FMC_LA08_P" LOC = W20 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 33
 #NET "FMC_LA08_N" LOC = Y21 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V  FMC_XM105 J1 pin 35
 #NET "FMC_LA09_P" LOC = R25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 37
 #NET "FMC_LA09_N" LOC = P25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V  FMC_XM105 J1 pin 39
 #NET "FMC_LA10_P" LOC = U24 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
+#CPU_Gnt
+set_property PACKAGE_PIN U24 [get_ports CPU_Gnt]
+set_property IOSTANDARD LVCMOS25 [get_ports CPU_Gnt]
+
 #NET "FMC_LA10_N" LOC = U25 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
+#CPU_Req
+set_property PACKAGE_PIN U25 [get_ports CPU_Req]
+set_property IOSTANDARD LVCMOS25 [get_ports CPU_Req]
+
 #NET "FMC_LA11_P" LOC = U26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
 #NET "FMC_LA11_N" LOC = V26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V
+#LED_ACT
+set_property PACKAGE_PIN V26 [get_ports LED_ACT]
+set_property IOSTANDARD LVCMOS25 [get_ports LED_ACT]
+
 #NET "FMC_LA12_P" LOC = R26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
 #NET "FMC_LA12_N" LOC = P26 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 13 VCCO - 2.5 V
 #NET "FMC_LA13_P" LOC = AE23 | IOSTANDARD = LVDS_25 | DIFF_TERM = "TRUE";    #Bank 12 VCCO - 2.5 V