Skip to content

S
SVEC BST Receiver
Commit 07edec49 authored by Tom Levens's avatar Tom Levens
Browse files
Options

Update for TTC_FMC V3

parent df314dad
Hide whitespace changes
Inline Side-by-side
Showing with 155 additions and 52 deletions
hdl/rtl/svec_top.vhd
View file @ 07edec49
......@@ -91,16 +91,34 @@ entity svec_top is
gpio34_a2b_o : out std_logic;
-- BST FMC
fmc_pg_c2m_o : out std_logic;
fmc_prsnt_m2c_n_i : in std_logic;
fmc_scl_b : inout std_logic;
fmc_sda_b : inout std_logic;
fmc_s1_o : out std_logic_vector(1 downto 0);
fmc_s2_o : out std_logic_vector(1 downto 0);
fmc_s3_o : out std_logic_vector(1 downto 0);
fmc_s4_o : out std_logic_vector(1 downto 0);
fmc_s41_sel_o : out std_logic;
fmc_2de_o : out std_logic;
fmc_3de_o : out std_logic;
fmc_div_div4_o : out std_logic;
fmc_div_rst_b_o : out std_logic;
fmc_trig_p_i : in std_logic;
fmc_trig_n_i : in std_logic;
fmc_clk0_m2c_p_i : in std_logic;
fmc_clk0_m2c_n_i : in std_logic;
fmc_cdr_dat_p_i : in std_logic;
fmc_cdr_dat_n_i : in std_logic;
fmc_fpga_scl_b : inout std_logic;
fmc_fpga_sda_b : inout std_logic;
fmc_user_led_n_o : out std_logic;
fmc_cdr_los_i : in std_logic;
fmc_cdr_lol_i : in std_logic
);
......@@ -127,23 +145,25 @@ architecture rtl of svec_top is
constant c_NUM_WB_MASTERS : integer := 1;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 2;
constant c_NUM_WB_SLAVES : integer := 3;
-- Wishbone master(s)
constant c_WB_MASTER_VME : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_ONEWIRE : integer := 0;
constant c_WB_SLAVE_BST : integer := 1;
constant c_WB_SLAVE_I2C : integer := 0;
constant c_WB_SLAVE_ONEWIRE : integer := 1;
constant c_WB_SLAVE_BST : integer := 2;
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) := (
0 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_bst_decoder_sdb, x"00002000"),
2 => f_sdb_embed_repo_url(c_repo_url_sdb),
3 => f_sdb_embed_synthesis(c_synthesis_sdb),
4 => f_sdb_embed_integration(c_integration_sdb)
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(5 downto 0) := (
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_bst_decoder_sdb, x"00002000"),
3 => f_sdb_embed_repo_url(c_repo_url_sdb),
4 => f_sdb_embed_synthesis(c_synthesis_sdb),
5 => f_sdb_embed_integration(c_integration_sdb)
);
------------------------------------------------------------------------------
......@@ -177,6 +197,14 @@ architecture rtl of svec_top is
signal one_wire_en : std_logic_vector(0 downto 0);
signal one_wire_i : std_logic_vector(0 downto 0);
-- FMC I2C
signal fmc_scl_in : std_logic_vector(1 downto 0);
signal fmc_scl_out : std_logic_vector(1 downto 0);
signal fmc_scl_oe_n : std_logic_vector(1 downto 0);
signal fmc_sda_in : std_logic_vector(1 downto 0);
signal fmc_sda_out : std_logic_vector(1 downto 0);
signal fmc_sda_oe_n : std_logic_vector(1 downto 0);
-- BST
signal cdr_clk : std_logic;
signal cdr_dat : std_logic;
......@@ -198,6 +226,8 @@ architecture rtl of svec_top is
signal bst_ext_trig : std_logic_vector(23 downto 0);
signal ext_trig : std_logic;
-- LEDs
constant c_LED_OFF : std_logic_vector(1 downto 0) := "00";
constant c_LED_RED : std_logic_vector(1 downto 0) := "10";
......@@ -212,10 +242,11 @@ architecture rtl of svec_top is
signal led6 : std_logic_vector(1 downto 0);
signal led7 : std_logic_vector(1 downto 0);
signal led8 : std_logic_vector(1 downto 0);
signal led_fmc : std_logic;
signal leds_x0 : std_logic_vector(15 downto 0);
signal leds_x1 : std_logic_vector(15 downto 0);
signal leds : std_logic_vector(15 downto 0);
signal leds_x0 : std_logic_vector(16 downto 0);
signal leds_x1 : std_logic_vector(16 downto 0);
signal leds : std_logic_vector(16 downto 0);
begin
......@@ -391,11 +422,46 @@ begin
one_wire_b <= '0' when one_wire_en(0) = '1' else 'Z';
one_wire_i(0) <= one_wire_b;
------------------------------------------------------------------------------
-- I2C master
-- FMC EEPROM I2C bus
-- FMC CDR I2C bus
------------------------------------------------------------------------------
cmp_fmc_i2c_master : xwb_i2c_master
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_interfaces => 2)
port map (
clk_sys_i => sys_clk_62_5,
rst_n_i => sys_rst_n,
slave_i => cnx_slave_in(c_WB_SLAVE_I2C),
slave_o => cnx_slave_out(c_WB_SLAVE_I2C),
desc_o => open,
scl_pad_i => fmc_scl_in,
scl_pad_o => fmc_scl_out,
scl_padoen_o => fmc_scl_oe_n,
sda_pad_i => fmc_sda_in,
sda_pad_o => fmc_sda_out,
sda_padoen_o => fmc_sda_oe_n);
-- Tri-state buffers for SDA and SCL
fmc_scl_b <= fmc_scl_out(0) when fmc_scl_oe_n(0) = '0' else 'Z';
fmc_fpga_scl_b <= fmc_scl_out(1) when fmc_scl_oe_n(1) = '0' else 'Z';
fmc_scl_in <= fmc_fpga_scl_b & fmc_scl_b;
fmc_sda_b <= fmc_sda_out(0) when fmc_sda_oe_n(0) = '0' else 'Z';
fmc_fpga_sda_b <= fmc_sda_out(1) when fmc_sda_oe_n(1) = '0' else 'Z';
fmc_sda_in <= fmc_fpga_sda_b & fmc_sda_b;
------------------------------------------------------------------------------
-- BST decoder
------------------------------------------------------------------------------
-- Differential input buffers for CDR
-- Differential input buffers
cmp_cdr_clk_buf : IBUFGDS
generic map (
DIFF_TERM => true,
......@@ -416,11 +482,27 @@ begin
I => fmc_cdr_dat_p_i,
IB => fmc_cdr_dat_n_i);
-- Configure FMC clock routing
fmc_s1_o <= "11"; -- CDR_CLK => PCB TP (R13)
fmc_s2_o <= "11"; -- CDR_CLK => JITTER_CLEANER
fmc_s3_o <= "11"; -- CDR_CLK => CLK1_M2C
fmc_s4_o <= "11"; -- CDR_CLK => CLK0_M2C
cmp_ext_trig_buf : IBUFDS
generic map (
DIFF_TERM => true,
IBUF_LOW_PWR => false,
IOSTANDARD => "DEFAULT")
port map (
O => ext_trig,
I => fmc_trig_p_i,
IB => fmc_trig_n_i);
-- Configure FMC
fmc_s1_o <= "11"; -- CDR_CLK => PCB TP (R5)
fmc_s2_o <= "11"; -- CDR_CLK => CLK1_M2C
fmc_s3_o <= "11"; -- CDR_CLK => CLK2_BIDIR
fmc_s4_o <= "11"; -- CDR_CLK => CLK0_M2C
fmc_s41_sel_o <= '0';
fmc_2de_o <= '0';
fmc_3de_o <= '0';
fmc_div_div4_o <= '0';
fmc_div_rst_b_o <= '0';
fmc_pg_c2m_o <= '1';
-- BST decoder core
cmp_bst_decoder : BstDecoder
......@@ -528,22 +610,26 @@ begin
led7 <= c_LED_GRN when bst_ext_trig(c_BST_INJ_BIT) = '1' else c_LED_OFF;
led8 <= c_LED_GRN when bst_ext_trig(c_BST_UA9_BIT) = '1' else c_LED_OFF;
led_fmc <= bst_ext_trig(c_BST_PPS_BIT);
-- Synchronise LEDs to system clock
p_leds_sync : process(sys_clk_62_5)
begin
if rising_edge(sys_clk_62_5) then
if (sys_rst = '1') then
leds_x0 <= x"0000";
leds_x1 <= x"0000";
leds_x0 <= '0' & x"0000";
leds_x1 <= '0' & x"0000";
else
leds_x0 <= led5 & led6 & led7 & led8 & led1 & led2 & led3 & led4;
leds_x0 <= led_fmc &
led5 & led6 & led7 & led8 &
led1 & led2 & led3 & led4;
leds_x1 <= leds_x0;
end if;
end if;
end process;
-- Extend LEDs to 100ms
g_leds_extend: for i in 0 to 15 generate
-- Extend LED pulses to 100ms
g_leds_extend: for i in 0 to 16 generate
cmp_leds_extend : gc_extend_pulse
generic map (
g_width => 6250000)
......@@ -565,9 +651,12 @@ begin
rst_n_i => sys_rst_n,
clk_i => sys_clk_62_5,
led_intensity_i => "1100100", -- in %
led_state_i => leds,
led_state_i => leds(15 downto 0),
column_o => led_column_o,
line_o => led_line_o,
line_oen_o => led_line_oen_o);
-- FMC user LED
fmc_user_led_n_o <= not leds(16);
end rtl;
hdl/svec_top.ucf
View file @ 07edec49
......@@ -275,17 +275,17 @@ NET "led_column_o[3]" IOSTANDARD = "LVCMOS33";
#NET "" LOC = B9; # FMC1 DP0_C2M_P
#NET "" LOC = A9; # FMC1 DP0_C2M_N
#NET "" LOC = N29; # FMC1 PG_C2M
#NET "" LOC = N30; # FMC1 PRSNT_M2C
#NET "" LOC = P28; # FMC1 SCL
#NET "" LOC = P30; # FMC1 SDA
NET "fmc_pg_c2m_o" LOC = N29; # FMC1 PG_C2M
NET "fmc_prsnt_m2c_n_i" LOC = N30; # FMC1 PRSNT_M2C
NET "fmc_scl_b" LOC = P28; # FMC1 SCL
NET "fmc_sda_b" LOC = P30; # FMC1 SDA
#NET "" LOC = AJ30; # FMC1 TCK
#NET "" LOC = AG30; # FMC1 TDI
#NET "" LOC = AF30; # FMC1 TDO
#NET "" LOC = AE25; # FMC1 TMS
#NET "" LOC = E16; # FMC1 CLK1_M2C_P
#NET "" LOC = D16; # FMC1 CLK1_M2C_N
#NET "fmc_clk1_m2c_p_i" LOC = E16; # FMC1 CLK1_M2C_P
#NET "fmc_clk1_m2c_n_i" LOC = D16; # FMC1 CLK1_M2C_N
NET "fmc_clk0_m2c_p_i" LOC = H15; # FMC1 CLK0_M2C_P
NET "fmc_clk0_m2c_n_i" LOC = G15; # FMC1 CLK0_M2C_N
......@@ -297,10 +297,10 @@ NET "fmc_clk0_m2c_n_i" LOC = G15; # FMC1 CLK0_M2C_N
#NET "" LOC = L12; # FMC1 LA28_P
#NET "" LOC = M13; # FMC1 LA27_P
#NET "" LOC = L14; # FMC1 LA26_P
NET "fmc_cdr_lol_i" LOC = F11; # FMC1 LA25_P
#NET "" LOC = F11; # FMC1 LA25_P
#NET "" LOC = G10; # FMC1 LA24_P
#NET "" LOC = M15; # FMC1 LA23_P
NET "fmc_cdr_los_i" LOC = F13; # FMC1 LA22_P
#NET "" LOC = F13; # FMC1 LA22_P
#NET "" LOC = G12; # FMC1 LA21_P
#NET "" LOC = F15; # FMC1 LA20_P
#NET "" LOC = G14; # FMC1 LA19_P
......@@ -312,17 +312,17 @@ NET "fmc_cdr_los_i" LOC = F13; # FMC1 LA22_P
#NET "" LOC = G18; # FMC1 LA13_P
#NET "" LOC = F21; # FMC1 LA12_P
#NET "" LOC = G20; # FMC1 LA11_P
#NET "" LOC = L21; # FMC1 LA10_P
NET "fmc_div_rst_b_o" LOC = L21; # FMC1 LA10_P
NET "fmc_cdr_dat_p_i" LOC = M20; # FMC1 LA09_P
#NET "" LOC = F23; # FMC1 LA08_P
#NET "" LOC = G22; # FMC1 LA07_P
#NET "" LOC = B25; # FMC1 LA06_P
#NET "" LOC = M19; # FMC1 LA05_P
NET "fmc_s2_o[0]" LOC = D24; # FMC1 LA04_P
NET "fmc_s3_o[1]" LOC = E25; # FMC1 LA03_P
NET "fmc_s4_o[1]" LOC = J22; # FMC1 LA02_P
#NET "" LOC = H21; # FMC1 LA01_P
NET "fmc_s4_o[0]" LOC = C16; # FMC1 LA00_P
NET "fmc_cdr_lol_i" LOC = F23; # FMC1 LA08_P
NET "fmc_fpga_scl_b" LOC = G22; # FMC1 LA07_P
NET "fmc_trig_p_i" LOC = B25; # FMC1 LA06_P
NET "fmc_s41_sel_o" LOC = M19; # FMC1 LA05_P
NET "fmc_s3_o[0]" LOC = D24; # FMC1 LA04_P
NET "fmc_s2_o[1]" LOC = E25; # FMC1 LA03_P
NET "fmc_s1_o[1]" LOC = J22; # FMC1 LA02_P
NET "fmc_2de_o" LOC = H21; # FMC1 LA01_P
NET "fmc_s1_o[0]" LOC = C16; # FMC1 LA00_P
#NET "" LOC = H12; # FMC1 LA33_N
#NET "" LOC = G11; # FMC1 LA32_N
#NET "" LOC = K11; # FMC1 LA31_N
......@@ -346,22 +346,28 @@ NET "fmc_s4_o[0]" LOC = C16; # FMC1 LA00_P
#NET "" LOC = F18; # FMC1 LA13_N
#NET "" LOC = E21; # FMC1 LA12_N
#NET "" LOC = F20; # FMC1 LA11_N
#NET "" LOC = K21; # FMC1 LA10_N
NET "fmc_div_div4_o" LOC = K21; # FMC1 LA10_N
NET "fmc_cdr_dat_n_i" LOC = L20; # FMC1 LA09_N
#NET "" LOC = E23; # FMC1 LA08_N
#NET "" LOC = F22; # FMC1 LA07_N
#NET "" LOC = A25; # FMC1 LA06_N
#NET "" LOC = L19; # FMC1 LA05_N
NET "fmc_s2_o[1]" LOC = C24; # FMC1 LA04_N
NET "fmc_s1_o[0]" LOC = D25; # FMC1 LA03_N
NET "fmc_s3_o[0]" LOC = H22; # FMC1 LA02_N
#NET "" LOC = G21; # FMC1 LA01_N
NET "fmc_s1_o[1]" LOC = A16; # FMC1 LA00_N
NET "fmc_cdr_los_i" LOC = E23; # FMC1 LA08_N
NET "fmc_fpga_sda_b" LOC = F22; # FMC1 LA07_N
NET "fmc_trig_n_i" LOC = A25; # FMC1 LA06_N
NET "fmc_user_led_n_o" LOC = L19; # FMC1 LA05_N
NET "fmc_s3_o[1]" LOC = C24; # FMC1 LA04_N
NET "fmc_s4_o[0]" LOC = D25; # FMC1 LA03_N
NET "fmc_s2_o[0]" LOC = H22; # FMC1 LA02_N
NET "fmc_s4_o[1]" LOC = G21; # FMC1 LA01_N
NET "fmc_3de_o" LOC = A16; # FMC1 LA00_N
NET "fmc_pg_c2m_o" IOSTANDARD = "LVCMOS33";
NET "fmc_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS33";
NET "fmc_scl_b" IOSTANDARD = "LVCMOS33";
NET "fmc_sda_b" IOSTANDARD = "LVCMOS33";
NET "fmc_clk0_m2c_p_i" IOSTANDARD = "LVDS_25";
NET "fmc_clk0_m2c_n_i" IOSTANDARD = "LVDS_25";
NET "fmc_cdr_dat_p_i" IOSTANDARD = "LVDS_25";
NET "fmc_cdr_dat_n_i" IOSTANDARD = "LVDS_25";
NET "fmc_trig_p_i" IOSTANDARD = "LVDS_25";
NET "fmc_trig_n_i" IOSTANDARD = "LVDS_25";
NET "fmc_s1_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc_s1_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc_s2_o[0]" IOSTANDARD = "LVCMOS25";
......@@ -370,5 +376,13 @@ NET "fmc_s3_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc_s3_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc_s4_o[0]" IOSTANDARD = "LVCMOS25";
NET "fmc_s4_o[1]" IOSTANDARD = "LVCMOS25";
NET "fmc_s41_sel_o" IOSTANDARD = "LVCMOS25";
NET "fmc_2de_o" IOSTANDARD = "LVCMOS25";
NET "fmc_3de_o" IOSTANDARD = "LVCMOS25";
NET "fmc_cdr_los_i" IOSTANDARD = "LVCMOS25";
NET "fmc_cdr_lol_i" IOSTANDARD = "LVCMOS25";
NET "fmc_user_led_n_o" IOSTANDARD = "LVCMOS25";
NET "fmc_div_div4_o" IOSTANDARD = "LVCMOS25";
NET "fmc_div_rst_b_o" IOSTANDARD = "LVCMOS25";
NET "fmc_fpga_sda_b" IOSTANDARD = "LVCMOS25";
NET "fmc_fpga_scl_b" IOSTANDARD = "LVCMOS25";
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment