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White Rabbit Trigger Distribution
Commit ef2ea508 authored by Tristan Gingold's avatar Tristan Gingold
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tdc: check presence of fmc.

parent 81ad6598
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Showing with 54 additions and 15 deletions
hdl/top/wrtd_ref_svec_tdc_x2/wrtd_ref_svec_tdc_x2.vhd
View file @ ef2ea508
......@@ -435,7 +435,7 @@ begin -- architecture arch
generic map (
g_VENDOR_ID => x"0000_10DC",
g_DEVICE_ID => c_WRTD_NODE_ID,
g_VERSION => x"0100_0000",
g_VERSION => x"0100_0001",
g_CAPABILITIES => x"0000_0000",
g_COMMIT_ID => (others => '0'))
port map (
......@@ -679,6 +679,7 @@ begin -- architecture arch
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
fmc_id_i => '0',
fmc_present_n_i => fmc0_prsnt_m2c_n_i,
pll_sclk_o => fmc0_tdc_pll_sclk_o,
pll_sdi_o => fmc0_tdc_pll_sdi_o,
pll_cs_o => fmc0_tdc_pll_cs_n_o,
......@@ -751,6 +752,7 @@ begin -- architecture arch
rst_sys_n_i => rst_sys_62m5_n,
rst_n_a_i => rst_sys_62m5_n,
fmc_id_i => '1',
fmc_present_n_i => fmc1_prsnt_m2c_n_i,
pll_sclk_o => fmc1_tdc_pll_sclk_o,
pll_sdi_o => fmc1_tdc_pll_sdi_o,
pll_cs_o => fmc1_tdc_pll_cs_n_o,
......
software/firmware/tdc-x2/Makefile
View file @ ef2ea508
......@@ -12,6 +12,8 @@ EXTRA2_CFLAGS += # To be set by user on make line
EXTRA_CFLAGS += $(EXTRA2_CFLAGS)
EXTRA_CFLAGS += -I$(CUR_DIR)/../../include -I$(CUR_DIR)/../common -I$(CUR_DIR)/../tdc
all:
# Redirect all rules to MockTurtle
%:
$(MAKE) -C $(WRTD_DEP_TRTL_FW) M=$(CUR_DIR) \
......
software/firmware/tdc/hw/fmctdc-direct.h
View file @ ef2ea508
......@@ -3,7 +3,7 @@
* File : fmctdc-direct.h
* Author : auto-generated by wbgen2 from fmc_tdc_direct_readout_slave.wb
* Created : Thu May 15 14:23:14 2014
* Created : Wed Mar 24 09:22:15 2021
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_tdc_direct_readout_slave.wb
......@@ -14,7 +14,11 @@
#ifndef __WBGEN2_REGDEFS_FMC_TDC_DIRECT_READOUT_SLAVE_WB
#define __WBGEN2_REGDEFS_FMC_TDC_DIRECT_READOUT_SLAVE_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
......@@ -35,6 +39,8 @@
/* definitions for register: Dead Time Register */
/* definitions for register: Status Register */
/* definitions for register: FIFO 'Readout FIFO' data output register 0 */
/* definitions for field: Seconds in reg: FIFO 'Readout FIFO' data output register 0 */
......@@ -85,12 +91,14 @@
#define DR_REG_CHAN_ENABLE 0x00000000
/* [0x4]: REG Dead Time Register */
#define DR_REG_DEAD_TIME 0x00000004
/* [0x8]: REG FIFO 'Readout FIFO' data output register 0 */
#define DR_REG_FIFO_R0 0x00000008
/* [0xc]: REG FIFO 'Readout FIFO' data output register 1 */
#define DR_REG_FIFO_R1 0x0000000c
/* [0x10]: REG FIFO 'Readout FIFO' data output register 2 */
#define DR_REG_FIFO_R2 0x00000010
/* [0x14]: REG FIFO 'Readout FIFO' control/status register */
#define DR_REG_FIFO_CSR 0x00000014
/* [0x8]: REG Status Register */
#define DR_REG_STATUS 0x00000008
/* [0xc]: REG FIFO 'Readout FIFO' data output register 0 */
#define DR_REG_FIFO_R0 0x0000000c
/* [0x10]: REG FIFO 'Readout FIFO' data output register 1 */
#define DR_REG_FIFO_R1 0x00000010
/* [0x14]: REG FIFO 'Readout FIFO' data output register 2 */
#define DR_REG_FIFO_R2 0x00000014
/* [0x18]: REG FIFO 'Readout FIFO' control/status register */
#define DR_REG_FIFO_CSR 0x00000018
#endif
software/firmware/tdc/hw/tdc_regs.h
View file @ ef2ea508
......@@ -23,10 +23,13 @@
#define TDC_REG_IRQ_TIMEOUT 0x0094
#define TDC_REG_DAC_TUNE 0x0098
#define TDC_REG_CURRENT_UTC 0x00a0
#define TDC_REG_BUFFER_PTR 0x00a8
#define TDC_REG_CTRL 0x00fc
#define TDC_REG_WR_CTRL 0x00b4
#define TDC_REG_CORE_STATUS 0x00ac
#define TDC_REG_WR_STAT 0x00b0
#define TDC_REG_WR_CTRL 0x00b4
#define TDC_REG_CTRL 0x00fc
#define TDC_CORE_STATUS_FMC_ID BIT(2)
#define TDC_CORE_STATUS_PRES BIT(3)
#define TDC_WR_CTRL_ENABLE BIT(0)
......
software/firmware/tdc/wrtd-tdc.c
View file @ ef2ea508
......@@ -14,7 +14,7 @@
#include "wrtd-tdc.h"
struct wrtd_tdc_calibration calib = {
static const struct wrtd_tdc_calibration calib = {
.offset_tai = { 0, 0, 0, 0, 0},
.offset_coarse = { -94, -94, -94, -94, -94},
.offset_frac = { 200, 200, 400, 400, 400},
......@@ -25,6 +25,8 @@ struct wrtd_tdc_dev {
uint32_t io_addr;
/* First channel for the TDC input 0. */
uint8_t ch;
/* True if FMC is present. */
uint8_t present;
};
static inline void tdc_writel(const struct wrtd_tdc_dev *dev,
......@@ -182,6 +184,7 @@ static inline void tdc_apply_calibration(struct wrtd_tdc_dev *tdc, int index)
static int tdc_init(struct wrtd_tdc_dev *tdc)
{
int err, i;
unsigned v;
pr_debug("%s: Initializing the TDC...\n\r", __func__);
......@@ -189,6 +192,15 @@ static int tdc_init(struct wrtd_tdc_dev *tdc)
tdc_writel(tdc, 0x0, BASE_DP_TDC_DIRECT + DR_REG_CHAN_ENABLE);
tdc_writel(tdc, DEFAULT_DEAD_TIME, BASE_DP_TDC_DIRECT + DR_REG_DEAD_TIME);
/* Check presence */
tdc->present = 1;
v = tdc_readl(tdc, BASE_DP_TDC_DIRECT + DR_REG_STATUS);
if (!(v & 1)) {
pr_debug("%s: ACAM not present\n",__func__);
tdc->present = 0;
return 0;
}
tdc_enable_acquisition(tdc, 0);
#ifndef SIMULATION
......@@ -222,16 +234,22 @@ static int tdc_init(struct wrtd_tdc_dev *tdc)
static inline int tdc_wr_link_up(struct wrtd_tdc_dev *tdc)
{
if (!tdc->present)
return 1;
return tdc_readl(tdc, BASE_DP_TDC_REGS + TDC_REG_WR_STAT) & TDC_WR_STAT_LINK;
}
static inline int tdc_wr_time_locked(struct wrtd_tdc_dev *tdc)
{
if (!tdc->present)
return 1;
return tdc_readl(tdc, BASE_DP_TDC_REGS + TDC_REG_WR_STAT) & TDC_WR_STAT_AUX_LOCKED;
}
static void tdc_wr_enable_lock(struct wrtd_tdc_dev *tdc, int enable)
{
if (!tdc->present)
return;
tdc_writel(tdc, TDC_CTRL_DIS_ACQ, BASE_DP_TDC_REGS + TDC_REG_CTRL);
tdc_writel(tdc, enable ? TDC_WR_CTRL_ENABLE : 0, BASE_DP_TDC_REGS + TDC_REG_WR_CTRL);
tdc_writel(tdc, TDC_CTRL_EN_ACQ, BASE_DP_TDC_REGS + TDC_REG_CTRL);
......@@ -239,6 +257,8 @@ static void tdc_wr_enable_lock(struct wrtd_tdc_dev *tdc, int enable)
static inline int tdc_wr_time_ready(struct wrtd_tdc_dev *tdc)
{
if (!tdc->present)
return 1;
return tdc_readl(tdc, BASE_DP_TDC_REGS + TDC_REG_WR_STAT) & TDC_WR_STAT_TIME_VALID;
}
......@@ -257,7 +277,8 @@ static void tdc_input(struct wrtd_tdc_dev *tdc)
struct wrtd_event ev;
int meta;
/* Poll the FIFO and read the timestamp */
/* Poll the FIFO and read the timestamp.
No need to check for presence: no channels enabled. */
if(fifo_sr & DR_FIFO_CSR_EMPTY)
return;
......@@ -265,6 +286,9 @@ static void tdc_input(struct wrtd_tdc_dev *tdc)
ev.ts.ns = tdc_readl(tdc, BASE_DP_TDC_DIRECT + DR_REG_FIFO_R1) * 8;
meta = tdc_readl(tdc, BASE_DP_TDC_DIRECT + DR_REG_FIFO_R2);
if (ev.ts.seconds == 0)
return;
/* Conversion from ACAM TDC bins to WR already done in gateware
(including overflow checks), result is in 2**-12 8ns ticks */
uint32_t frac = meta & 0x00fff;
......
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