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White Rabbit Trigger Distribution
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White Rabbit Trigger Distribution
Commits
e9a19175
Commit
e9a19175
authored
Jan 16, 2019
by
Tristan Gingold
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Add syn/spec_adc
parent
f0db8a01
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Manifest.py
builder/hdl/syn/spec_adc/Manifest.py
+36
-0
spec_adc.ucf
builder/hdl/syn/spec_adc/spec_adc.ucf
+522
-0
syn_extra_steps.tcl
builder/hdl/syn/spec_adc/syn_extra_steps.tcl
+26
-0
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builder/hdl/syn/spec_adc/Manifest.py
0 → 100644
View file @
e9a19175
# HDLMake 'develop' branch required.
#
# Due to bugs in release v3.0 of hdlmake it is necessary to use the "develop"
# branch of hdlmake, commit db4e1ab.
board
=
"spec"
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx100t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_adc_top"
syn_project
=
"spec_adc.xise"
syn_tool
=
"ise"
fetchto
=
"../../../../dependencies"
ctrls
=
[
"bank3_64b_32b"
]
syn_post_project_cmd
=
(
"$(TCL_INTERPRETER) "
+
\
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
\
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
files
=
[
"spec_adc.ucf"
,
]
modules
=
{
"local"
:
[
"../../top/spec_adc"
,
],
}
builder/hdl/syn/spec_adc/spec_adc.ucf
0 → 100644
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e9a19175
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builder/hdl/syn/spec_adc/syn_extra_steps.tcl
0 → 100644
View file @
e9a19175
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
if
{
!
[
file
exists
$project
_file
]}
{
report ERROR
"Missing file
$project
_file, exiting."
exit -1
}
xilinx::project open
$project
_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"2"
-process
"Map"
xilinx::project set
"Enable Multi-Threading"
"4"
-process
"Place & Route"
xilinx::project set
"Pack I/O Registers into IOBs"
"Yes"
xilinx::project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
xilinx::project set
"Register Balancing"
"Yes"
xilinx::project set
"Register Duplication Map"
"On"
xilinx::project save
xilinx::project close
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